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MOSFET SOI MOSFET SOI Advantages SOI Basic Features/Problems Five Topics Studied

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MOSFET SOI MOSFET SOI Advantages SOI Basic Features/Problems Five Topics Studied

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  1. Studies on Channel Coupling and Floating Body Effects and Their Impacts on Device Performance and Reliability in SOI MOSFETPresenter: Franklin L. DuanPh.D. Advisor: Prof. D.E. IoannouDepartment of Electrical & Computer EngineeringSchool of Information Technology and Engineering George Mason UniversityFairfax, Virginia

  2. Outline • MOSFET • SOI MOSFET • SOI Advantages • SOI Basic Features/Problems • Five Topics Studied • Summary of the Results

  3. Tree of Information Technology S I T E IT: Information Technology Information Technology Soft Solid Device Circuit Others MOSFET

  4. MOSFET (Metal Oxide Silicon Field Effect Transistor) Gate Drain Source Metal Oxide Silicon

  5. Scaling-down Rule of MOSFET

  6. Moore’s Law of VLSI

  7. Side Effects of Scaling-down • Hot carrier degradation due to the increased electric field and hot carrier injections • Lowered circuit speed due to the lower driving current and higher capacitance

  8. SOI (Silicon On Insulator) MOSFET G1 S D P N+ N+ Si BOX Si G2

  9. SOI Advantages • Radiation hardness • Low power/high speed • Reduction in parasitic capacitance • Improved subthreshold slope • Improved short channel effect • CMOS latch-up free • Increased ULSI packing density • Simplified fabrication

  10. Dual Gate control Channel Coupling Floating Body Effect SOI Three Basic Features in Device Physics

  11. Three Basic Features of SOI G1 2 3 1 G2

  12. Five Topics Studied in the Thesis • Dual gate control: • Opposite channel based-hot-carrier injection (OCBI) technique, unique tool for hot carrier study in SOI • Channel coupling: • trade-off between hot carrier degradation and FBE • Floating Body Effect (FBE): • abnormally higher impact ionization rate at the edges • Two modes of operations in FD SOI: • a new mixed mode structure • Bulk technology integration: • performance and reliability trade-off

  13. Experimentally hot carrier stressing substrate current (as a monitor of degradation) measurement single transistor latch up voltage characterization By simulation map: electric potential electric field, current path, calculate : hot carrier generation hot carrier injection current Methodology/ Characterization

  14. 1. OCBI Technique(Opposite Channel Based Injection) VG1= 1 V VS= 0 V VD= 7 V - + - P N+ N+ Ih VG2= -30 V

  15. Pure Hole Injection Into the BOX Ih2: hole injection current Ie2: electron injection current VD=7V, VG2= -30V.

  16. Shift of Characteristics After Hole Injection 10 hrs stressing Original

  17. D - V T2 Back Threshold Voltage Shift ( ) as a Function of Stress Time Standard SIMOX With a supplemental O2 implantation

  18. 2. Channel Coupling

  19. Channel Coupling Effect on Hot Carrier Temperature, Impact Generation and Electric Field

  20. Substrate Current Dependence on the Back Gate Bias in FD SOI MOSFET

  21. Substrate Current Dependence on the Back Gate Bias in PD SOI MOSFET

  22. Channel Coupling Effect onHot Carrier Degradation

  23. Channel Coupling Effect on Single Transistor Latch-up

  24. Impact Generation Rate as a Function of Silicon Film Thickness Ts=0.25um 0.3um 0.4um 0.8um (bulk)

  25. VC n+ p SiO2 n+ W VE 3. Study of Floating Body Effect (FBE) its Edge and Width Effect

  26. Contour Plot of Impact Generation Rate for Different Channel Width

  27. Abnormally Higher Impact Generation Rate at the Edges

  28. Impact Generation Rate at the Edges When the Body is Grounded um um

  29. Single Transistor Latch-up Voltage as a Function of Device Width

  30. Hot Carrier Degradation of Three Devices with Different Width

  31. Kink Effect Dependence on Channel Width

  32. 4. A New FD SOI MOSFET Structure

  33. Two existing FD SOI MOSFETs P+ N+ N- P N+ N+ N+ N+ INV: inversion mode ACC: accumulation mode

  34. Potential Profiles of the Inversion and Accumulation Mode FD SOI MOSFET

  35. (mm) -0.2 spacer p-poly -0.1 0.0 n-type n+ n+ p-type 0.1 BOX (mm) 0 0.4 0.8 1.2 Virtually Fabricated New SOI Device (by SUPREM)

  36. Comparison of Transconductance and Latch-up Voltage of the Three Devices

  37. Comparison of the Hot Carrier Injection of the Three Devices Ih1 Ie1 Ie2 Ih2 A

  38. 5. LDD Design Tradeoff in SOI MOSFET (A) (B) (C)

  39. Experimental Results: Tradeoff Between Performance and Reliability)

  40. Contours of Impact Generation Rate of the Three LDD Designs

  41. Comparison of Impact Generation Rate and Latch-up Voltage

  42. Summary of the Results • Opposite channel based injection can happen by the aid of dual gate control and this phenomenon can be used as a tool to study the hot carrier degradation • Channel coupling imposes a trade-off between the hot carrier reliability and single transistor latch-up in SOI MOSFET • The rate of carrier generation rate is higher at the edge of SOI MOSFET and more so for wider devices. Wider devices have lower breakdown voltages. • A new structure was proposed which holds the weaknesses of the current FD SOI MOSFETs and is more resistant to hot carrier injections • Optimized bulk LDD technology faces a tradeoff between hot carrier reliability and single transistor latch-up in SOI MOSFET

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