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Quiz 3 .1

  Compiler friendly   Larger code sizes (~30 %)   Complicated microcode   Fewer instructions   Easier to validate   Emphasis on hardware   Emphasis on software   Memory to memory operations   Pipelining friendly. Quiz 3 .1.

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Quiz 3 .1

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  1.   Compiler friendly   Larger code sizes (~30%)   Complicated microcode   Fewer instructions   Easier to validate   Emphasis on hardware   Emphasis on software   Memory to memory operations   Pipelining friendly Quiz 3.1 • What best differentiates RISC and CISC architectures? CISC RISC

  2. Quiz 3.2 1. What is an ISA? 2. What is a memory address space? 3. What is memory addressability? 4. What is a computer port? 5. List some distinctive properties of the MSP430 ISA.

  3. Quiz 3.3 • How are the sixteen MSP430 registers the same? • How do they differ? • What does 8-bit addressibility mean? • Why does the MSP430 have a 16-bit data bus? • What does the “addc.w r11,r12” instruction do?

  4. Quiz 3.4 • What is the length (in words) and cycles for each of the following instructions? 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20.

  5. Quiz 3.5 Disassemble the following MSP430 instructions: AddressData 0x8010: 4031 0x8012: 0600 0x8014: 40B2 0x8016: 5A1E 0x8018: 0120 0x801a: 430E 0x801c: 535E 0x801e: F07E 0x8020: 000F 0x8022: 1230 0x8024: 000E 0x8026: 8391 0x8028: 0000 0x802a: 23FD 0x802c: 413F 0x802e: 3FF6

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