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Πρόγραμμα Αναβάθμισης Προγράμματος Σπουδών Τμήματος Πληροφορικής Τ.Ε.Ι Θεσσαλονίκης PowerPoint PPT Presentation


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Πρόγραμμα Αναβάθμισης Προγράμματος Σπουδών Τμήματος Πληροφορικής Τ.Ε.Ι Θεσσαλονίκης. Μάθημα Οργάνωση και Αρχιτεκτονική Υπολογιστών Κεφαλαίο Έκτο Ο προγραμματισμός στη συμβολική γλώσσα μηχανής του ΜΙΧ 1009 Μέρος πρώτο Καθηγητής: Α. Βαφειάδης 200 8. Βασικοί συντακτικοί κανόνες.

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Πρόγραμμα Αναβάθμισης Προγράμματος Σπουδών Τμήματος Πληροφορικής Τ.Ε.Ι Θεσσαλονίκης

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5691482

..

1009

: .

2008


5691482

  • Top-down-programming


5691482

  • LDA PAR1 REG[A] <-- REG[A] + MEM[PAR2]

    ADD PAR2 REG[A] <-- MEM[PAR1]

    STA RES MEM[RES] <-- REG[A]

  • LDA PAR1 REG[A] <-- MEM[PAR1]

    SUB PAR2 REG[A] <-- REG[A] - MEM[PAR2]

    STA RES MEM[RES] <-- REG[A]

  • LDA PAR1 REG[A] <-- MEM[PAR1]

    MUL PAR2 REG[AX] <-- REG[A] x MEM[PAR2]

    STX RES MEM[RES] <-- REG[X]

    < 230-1


5691482

  • * (A )

    LDX PAR1 rAX

    LDA PAR1(0:0) rAX

    DIV PAR2

    * ( )

    LDA PAR1 PAR1 rA

    SRAX 5

    DIV PAR2


5691482

1

  • W = P + * I

    LDA K rA <----- K

    MUL I rAX K * I

    SLAX 5 rA <------ rX

    ADD P rA P + K * I

    STA W H W P + K * I

    SLAX

    LDA K rA <----- K

    MUL I rAX K * I

    STX HELP HELP <----- rX

    LDA HELP rA K * I

    ADD P rA P + K * I

    STA W H W P + K * I


5691482

2

  • W = P (k*I)/D

    LDA K rA <------ K

    MUL I rAX K*I

    DIV D rA (K*I)/D

    SUB P rA (k*I)/D-P

    STA W W <------ (K*I)/D-P

    LDAN W rA P-(K*I)/D

    STA W W <------ P-(K*I)/D


5691482

3

  • W = (A+B)*(L-M)+2+(A-b)/Z

    * OVERFLOW

    * rA = rX /

    *

    LDA A

    ADD B (+)

    STA H

    LDA L (L-M)

    SUB M

    MUL H rAX (A+B)*(L-M)

    INCX 2 rA (+)*(L-M)+2

    STX H

    LDA A r <------

    SUB r -

    SRAX 5 r -

    * ( rA)

    DIV Z r (-)/

    ADD H r (+)*(L-)+2+(-)/

    STA W W (+)*(L-)+2+(-)/


5691482

4

  • W = (M-L)*(L/Z) # 0

    LDAMrA <---------- M

    SUBLrA M-L

    STA H M-L

    LDAKrA <---------- K

    SRAX 5 rAX <---------- K

    DIV Z rA <---------- K/Z

    MUL H rAX (M-L)*(K/Z)

    STX W W <---------- (M-L)*(K/Z)

    (M-L)*(K/Z) = ((M-L)*K)/Z).

    LDA M rA <-------- M

    SUB L rA M-L

    MUL K rAX (M-L)*K

    DIV Z rAX ((M-L)*K)/Z

    STA W W <-------- ((M-L)*K


5691482

    • Hardware


Hardware

Hardware

  • JOV

    = ""

    "FF"

    J PC

    PC JOV

  • JNOV

    = "FF"

    J PC

    PC JOV

    "FF"


Hardware 1

Hardware 1

LDAMrA <-------- M

SUBLrA M-L

MULKrAX (M-L)*K

DIVZ rAX ((M-L)*K)/Z

JOV OFLOW

STA W W <-------- ((M-L)*K

.....

OFLOW

LT

(JNOV):

LDAMrA <-------- M

SUB L rA M-L

MUL K rAX (M-L)*K

DIV Z rAX ((M-L)*K)/Z

JNOV NFLOW

... M

....... ()

LT

NFLOW STA W W <-------- ((M-L)*K


5691482

()

OUTPUT ORIG *+24 OUTPUT BUFFER

MESSAGE ALF

ALF MESSAGE

ALF 3

. . . . . . . .

LDA PAR1 REG[A] <-- MEM[PAR1]

MUL PAR2 REG[AX] <-- REG[A] x MEM[PAR2]

JANZ OFLOW rA <> 0 OFLOW

STX RES MEM[RES] <-- REG[X]

. . . . . . . .

FLOW NOP

* M MESSAGE OUTPUT

LDA MESSAGE

STA OUTPUT

LDA MESSAGE+1

STA OUTPUT+1

LDA MESAGE+2

STA OUTPUT+2

*

OUT OUTPUT(LP)

JBUS *(LP)

HLT

END BEGIN


5691482

1 QU 1

2 CON 10

3 EQU 1

.....

1 1 rI1 <----- M1

LOOP NOP

.....

.....

INC1 3 rI1 <--- rI1 + 3

CMP1 M2 2

JLE LOOP


5691482

ENT1 0,5 r1 <----- rI5

LOOP NOP

.....

.....

INC1 0,6 rI1 <----- rI1 + rI6

CMP1 2 2

JLE LOOP

= + REG()

REG(1) = 0 + REG(5) --- REG(1) = REG(5)


5691482

  • 1 10.

    CON 10

    .....

    ENT1 1 r1 <---- 1 ( )

    ENTA 0

    LOOP INC 0,1 rA <---- rA + rI1

    C1 1 rI1 <---- rI1 + 1

    CMP1

    JLE LOOP


5691482

0

1

2

3

4

5

6

7

10

11

12

13

1 PIN

2

3

4

5

6

ORIG 3

PINORIG *+6

PIN-1,I

LDA PIN-1,4

. ( rI4 )

REG(4) 5

V= m +REG(4)=PIN-1+REG(4)= 3-1+5= 7 .


5691482

  • 100 . .

    N CON 100

    TWO CON 2

    SUMM CON 0

    SUMZ CON 0

    PIN ORIG *+100

    *

    BEGIN .....

    .....

    ENT1 1

    LP2 LDA PIN-1,1

    SRAX 5

    DIV TWO 2

    JXZ LP1

    LDA SUMM

    ADD PIN-1,1

    STA SUMM SUMM

    JMP LP3

    LP1 LDA SUMZ

    ADD PIN-1,1

    STA SUMZ SUMZ

    LP3 INC1 1

    CMP1 N

    JLE LP2

    .....


5691482

:

0000

TWO0001

SUMM0002

SUMZ0003

PIN0004

BEGIN0150

..

:

00000 00 00 00 01 44N

00010 00 00 00 00 02 TWO

00020 00 00 00 00 00SUMM

00030 00 00 00 00 00SUMZ

00040 00 00 00 00 00PIN 1

00050 00 00 00 00 00 2

00060 00 00 00 00 00 3

...........................................................

01470 00 00 00 00 00 100

0150


5691482

BEGIN .....

.....

ENT1 1

LDA PIN-1,1

SRAX 5

DIV TWO 2

JXZ *+5

LDA SUMM

ADD PIN-1,1

STA SUMM SUMM

JMP *+4

LDA SUMZ

ADD PIN-1,1

STA SUMZ SUMZ

INC1 1

CMP1 N

JLE *-13

.....


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