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Power Minimization using Simultaneous Gate Sizing, Dual-Vdd and Dual-Vth Assignment

Power Minimization using Simultaneous Gate Sizing, Dual-Vdd and Dual-Vth Assignment. Ashish Srivastava, Dennis Sylvester, David Blaauw. Outline. Introduction Preliminary Algorithm Experimental Results Conclusions. Introduction. Gate size => Delay Power V DD => Delay Power

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Power Minimization using Simultaneous Gate Sizing, Dual-Vdd and Dual-Vth Assignment

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  1. Power Minimization using Simultaneous Gate Sizing, Dual-Vdd and Dual-Vth Assignment Ashish Srivastava, Dennis Sylvester, David Blaauw

  2. Outline • Introduction • Preliminary • Algorithm • Experimental Results • Conclusions

  3. Introduction • Gate size => Delay Power • VDD => Delay Power • VTH => Delay Power

  4. Outline • Introduction • Preliminary • Dual Vdd constraint • Cluster Voltage Scaling (CVS) • Algorithm • Experimental Results • Conclusions

  5. VDDH VDDL Dual Vdd Constraint ON MP1 0 1 Static current N1 MN1 VDDL<VDDH-|Vtp|=>PMOS can not be cut-off

  6. 1 2 8 10 5 3 7 9 Cluster Voltage Scaling (CVS) Level Converter VDDH VDDL i1 LC o1 LC o2 i2 4 6 i3 LC o3 LC o4 i4 i5

  7. Cluster Voltage Scaling (CVS) Order by Capacitance or Slack {O1,o2,o3,o4} 1 i1 5 3 o1 8 9 o2 2 i2 4 6 10 i3 o3 7 o4 i4 i5 VDDH VDDL

  8. Outline • Introduction • Preliminary • Algorithm - VVS • Backward Pass • Frontward Pass • Experimental Results • Conclusions

  9. Outline • Introduction • Preliminary • Algorithm • Backward Pass • Frontward Pass • Experimental Results • Conclusions

  10. Backward Pass • Change cells from high VDD to low VDD • Dual Vdd & single Vth

  11. Backward Pass • Step1 CVS • without gate upsizing • Step2 • with gate upsizing

  12. 8 4 6 Backward Pass • Step1 CVS 1 2 5 7 3 VDDH VDDL

  13. 3 4 2 6 Backward Pass • Step 2 • Backward front High Vdd Gate Upsizing 8 Slack 1 5 7 VDDH VDDL

  14. Backward Pass • Escape local minima. Find the globe minima. • The front between high and low Vdd gates is in the best position in terms of the total power dissipation for a dual Vdd, single Vth.

  15. Outline • Introduction • Preliminary • Algorithm • Backward Pass • Frontward Pass • Experimental Results • Conclusions

  16. Forward Pass Create timing slack Select a gate to high Vdd or upsizeing Set gates to high Vth No Yes Power Reduce? Accept this move Reverse this move

  17. Forward Pass • How to select a gate to high Vdd or to up-sizing?

  18. Forward Pass • How to select a gate to high Vth?

  19. Outline • Introduction • Preliminary • Algorithm • Experimental Results • Conclusions

  20. Experimental Results

  21. Experimental Results The nominal activity is adjusted such the leakage power constitutes approximately 8% of the total power dissipation.

  22. Experimental Results

  23. Outline • Introduction • Preliminary • Algorithm • Experimental Results • Conclusions

  24. Conclusions • The VVS algorithm combines gate sizing with Vdd and Vth assignment to minimize the total power dissipation.

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