Pic 16f877
Download
1 / 17

PIC 16F877 - PowerPoint PPT Presentation


  • 61 Views
  • Uploaded on

PIC 16F877. Architectural Features :-. Harvard Architecture Reduced Instruction Set Long word Instructions Single Word Instructions Single Cycle Instructions Instruction Pipelining Register File structure Orthogonal (Symmetric) Instruction. Von Neumann. Harvard Architecture.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' PIC 16F877 ' - edward-collier


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

Architectural features

Architectural Features :-

Harvard Architecture

Reduced Instruction Set

Long word Instructions

Single Word Instructions

Single Cycle Instructions

Instruction Pipelining

Register File structure

Orthogonal (Symmetric) Instruction


Harvard architecture

Harvard Architecture

  • Common Program & Data Memories

  • Single Bus for both program & Data

  • Reduced Bandwidth

  • Multiple access through single Bus

  • Separate Program & Data Memories

  • Separate Buses

  • Improves Bandwidth

  • Single access through wider Program Bus & Program memory


Long word instructions
Long Word Instructions:

  • Long word instructions have a wider Instruction bus Width of bus indicates the width of memory. In case of Von neumann, instruction can be of 8 bits only. In case of Harvard, instruction can be of upto 14 bits. Here, Program memory width is optimized to meet architectural requirements.


Single word instruction
Single Word Instruction:

  • Harvard Architecture: Opcodes are 14 Bit wide  Single word instructions are possible. Fetches the whole word in single cycle b’coz width of IB is 14 bit. No. of program memory locations = No. of Instructions.Von – Neumann: Opcodes are 8 Bit wide  Single word instructions is not possible. Multiple Access is required to fetch 14 – bit wide instructions. No. of Instructions that can be stored = No. of Program Memory locations / 2


Instruction pipelining
Instruction Pipelining:

  • Harvard Architecture: 2 stage Pipeline : Fetch & Execute. For Fetch  1 instruction cycle = Tcy For Execute  1 instruction cycle = Tcy Due to overlap, of fetch2 of current instruction and Execute1 of the previous instruction, instruction execution time = TcyVon – Neumann: No Pipelining No Overlapping  Instruction execution time = 2 * Tcy.


Single cycle instruction
Single Cycle Instruction:

  • Harvard Architecture: As program memory bus is 14 bit wide, whole instruction can be executed in single cycle. There may be a delay of 1 instruction cycle ( Tcy), if result of the instruction is modified.Von – Neumann: Multicycle Instruction.


Reduced instruction set
Reduced Instruction Set:

  • Harvard Architecture: Instructions are well designed and orthogonal (Symmetric). So , fewer instructions are required to perform the needed task.Von – Neumann: More no. of Instructions  CISC.


Register file architecture
Register File Architecture:

  • Harvard Architecture: Registers are part of data memory that can be accessed directly or indirectlyVon – Neumann: More no. of Instructions  CISC.


Orthogonal instructions
Orthogonal Instructions:

  • Harvard Architecture: Orthogonal instructions makes it possible to carry out any operation on any register using any addressing mode. “Special Instructions”  makes programming more simple. Mid range instructions : SLEEP : Places the device in lower power mode. CLRWDT : Verifies the chip is operating properly or not by preventing the on chip Watch Dog Timer (WDT) from overflowing and resetting the device.




Memory

Page 0

Bank 0

0000h

07FFh

00h

000h

07Fh

Page1

Bank 1

080h

0FFh

0800h

0FFFh

Bank 2

Page 2

1000h

17FFh

100h

17Fh

Page 3

Bank 3

180h

1FFh

07h

1800h

1FFFh

Memory

Program

Memory

(8k x 14bit)

Stack

Memory

(8 x 14bit)

Data

Memory

(512 x 8bit)


Central processing unit
Central Processing Unit:

  • CPU is the brain of the processor. It performs the fetching of the instructions from program memory, decoding of the instruction and execution of the instructions. CPU uses the instructions stored in program memory. Some of the instructions needs data. To make the operations on the data, ALU is required. In addition to the Arithmatic and logical operations, ALU controls the status bits in STATUS Registers.



ad