Loading in 5 sec....

Lecture 2 Design AbstractionPowerPoint Presentation

Lecture 2 Design Abstraction

- 89 Views
- Uploaded on

Download Presentation
## PowerPoint Slideshow about ' Lecture 2 Design Abstraction' - edmund

**An Image/Link below is provided (as is) to download presentation**

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript

### Lecture 2Design Abstraction

Prepare Reading 1:(for lecture 3)An Introduction to

Asynchronous Circuit Design

Design Abstraction

English

executable

program

Register Transfer

Language

gates

transistors

rectangles

specification

system throughput

design time

function units

clock cycles

literals

gate depth

nanoseconds

microns

behavior

RTL

logic

circuit

layout

CAD Tools

specification

Cadence,

Synopsis,

Mentor Graphic,

Viewlogic,

Java, C++, ..

VHDL, Verilog, ..

SIS

SPICE, TimeMill,..

Magic, Layout Editor,

Tanner, ...

behavior

RTL

logic

Realization

and

Complexity

circuit

layout

RTL : VHDL

Architecture RTL of NAND2 is

begin

process (A,B)

begin

if (A=‘1’) and (B=‘1’) then

Z<=‘0’;

else

Z<=‘1’;

endif;

end process;

end RTL

A

B

Z

Gate level

- Netlist
- (and A (or B C))

CMOS : NAND

A

B

- NAND

C=(AB)’

C

(1) A=1 B=1 C=0 (2) A=0 B=0 C=1 (3) A=1 B=0 C=1

B

B

B

A

A

A

C

C

C

A

A

A

B

B

B

Muller C-element

- Transition diagram

- Symbol

A

B

A

B

C

C

- True Table

A B C

0 0 0

1 0 unchanged

0 1 unchanged

1 1 1

Muller C-element

- C-element CMOS implementation

A=0 B=1 C=unchanged

A=1 B=0 C=unchanged

A

B

A

B

C

C

A

B

A

B

Download Presentation

Connecting to Server..