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A Readout System-on-Chip for a Cubic Kilometer Submarine Neutrino Telescope

S.Anvar , V.Gautard , H.Le Provost , F.Louis , K.Menager , Y.Moudden , B.Vallage , E.Zonca , on behalf of the KM3NeT consortium 1 IRFU/SEDI-CEA Saclay F-91191 Gif-sur-Yvette, France 1 Supported by the European Commission through FP6 and FP7.

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A Readout System-on-Chip for a Cubic Kilometer Submarine Neutrino Telescope

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  1. S.Anvar, V.Gautard, H.Le Provost, F.Louis, K.Menager, Y.Moudden, B.Vallage, E.Zonca, on behalf of the KM3NeT consortium1 IRFU/SEDI-CEA Saclay F-91191 Gif-sur-Yvette, France 1Supported by the European Commission through FP6 and FP7 A Readout System-on-Chip for a Cubic Kilometer Submarine Neutrino Telescope TWEPP-11, Vienna, Austria, 26-30 September 2011

  2. The KM3Net Detector Digital Optical Module (DOM) 31 PMTs/DOM 12800 DOMs 320 lines http://www.km3net.org Technical Design Report (ISBN 978-90-6488-033-9)Conceptual Design Report (ISBN 978-90-6488-031-5)

  3. The DOM processor board Heat conductor Power conversion board PMT Processor board & Software designed at CEA-IRFU DOM designed at NIKHEF institute (Amsterdam, Netherlands) HV PMT base Signal collection board

  4. The KM3Net prototype Offshore Processor Board 31 x 1 GHz TDC Readout System On Chip (RSOC) / VIRTEX-5 31 TOT Data Readout Logic PMTs PPC440 processor x 31 small PMTs Data Task FPGA Bitstream / Processor Boot Data Slow Control Task RTOS Slow Control Clock /Command Extraction SC Protocol Logic Flash Memory (32 MB) DDR2 Memory (64 MB) Slow-Control for the Storey (I2C, SPI) 1Gb/s Ethernet Link To shore station

  5. Firmware TDC Development Packetized and Sent over ETHERNET Coarse Time Stamp #24-bit Event type/TDC number TDC #16-bit XILINX VIRTEX-5 ISERDES 0 0 1 0 1 0 1 0 8-bit 1 GHz Sampling Readout Logic @125 MHz ‘1’ Detection & Coarse Time Stamping 0 TOT LVDS PMT asynchronous input 0 0 PLL 500 MHz /500 MHz 125 MHz 1 Recovered ETHERNET Clock @125MHz 1 1 0 0 [Originally designed by A.Zwart (NIKHEF) / small PMTs test bench for ALTERA]

  6. Clock distribution Off Shore VIRTEX-5 RSOC On Shore VIRTEX-6 Board Command(CMD) extraction Command (CMD) insertion Transmit Reference Clock @62.5 MHz Embedded 62.5 MHz PPC440 Bus CMD Custom Logic DATA IDLE CMD Custom Logic DATA STANDARD 1000BASE-X ETHERNET 1.25 Gbps Event Time Stamping IDLE Phase and Latency Measurements Recovered Clock @62.5 MHz / Bit slice analysis (known latency)

  7. Transmit/Receive clock skew DMTD (Dual Mixer Time Difference) Scope Tx/Rx clock skew measured on shore with DMTD and oscilloscope (ns)

  8. Store & Forward Acquisition model Dynamic Memory 134 ms 31 TDC & Routing Matrix TDC event format (6 bytes) FIFO 0 Circular Buffer FIFO 0 PMT 0-31 DATA ROUTER FIFO 5 134 ms Acoustic Event Format (128 bytes) Readout Logic Acoustic Data FIFO 6 Circular Buffer FIFO 6 Detector Clock (ETHERNET) Interrupt @134 ms (Typical) Slow control (Configuration, Readout on requests) PPC440 processor @ 300 MHz 1 Gb/s Ethernet Port 134 ms Data 134 ms Data Slow Control Objects Time Slice To computer 2 Time Slice To Computer 1

  9. IntrinsicParallelism Time Slice Building EmbeddedComputing Time Slice 2 OffshoreNodes Time Slice 1 Time Slice 0 Start Clock Distribution/Commands Insertion • Detector Clock • (Start) Commands • Track reconstruction • Data routing Performance Parallelism Multi-gigabit Standard Ethernet Switching OnshoreFarm FarmComputing

  10. Electronics control & config Network Embedded Embedded TargetSC Server TargetSC Server Communication middleware (ICE) Electronics Control & Config (SC & Elec. RC) RunControl Data routers / writer Communicationmiddleware (ICE)

  11. Data acquisition setup Host PC On Shore VIRTEX-6 Board • Run Control • Target Configuration • Data acquisition • vxWorks RTOS boot server STANDARD 1000BASE-X ETHERNET Synchronous 1000BASE-X ETHERNET Pulse generator • RSOC VIRTEX5FX-70 • vxWorks RTOS • 1 TDC Channel • 1 dedicated TDC ASIC channel • PPC440@300 MHz Bus@75 MHz Start Command Reference Clock @62.5 MHz

  12. Acquisition results Scope measurement Mean : 100,10667 us RMS : 1,75 ns ns ns 8 ns 2 ns 2 ns Pulse @ f=10 kHz Power : 7 W Current acquisition setup (Source limitation): 60 Mb/s Standalone measured TCP/IP throughput PPC440@400 MHz / Bus@100 MHz /WindRiver Zero Copy buffer /Jumbo frames : 988 Mb/s

  13. CONCLUSION • Common Readout system functions integrated in a single component (RSOC): • Event Time stamping @ 1 GHz • Clock and command distribution • Slow-control and data acquisition performed in a RTOS multi-tasking embedded system • RSOC is a node designed to be plugged in a complete Data acquisition System • Server/Client topology (ICE) • Scalable system

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