Interfacing devices to the 68000
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Interfacing Devices to the 68000. Interfacing devices. Read cycle timing parameters. Write cycle timing parameters Memory Device parameters Other device issues. Read cycle timing. For interfacing the arrows matter Indicate the precedence of signals for interfacing. Timing continued.

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Interfacing Devices to the 68000

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Interfacing devices to the 68000

Interfacing Devices to the 68000

Lecture 12 - Interfacing Devices


Interfacing devices

Interfacing devices

  • Read cycle timing parameters.

  • Write cycle timing parameters

  • Memory Device parameters

  • Other device issues

Lecture 12 - Interfacing Devices


Read cycle timing

Read cycle timing

  • For interfacing the arrows matter

  • Indicate the precedence of signals for interfacing

Lecture 12 - Interfacing Devices


Timing continued

Timing continued

  • For a slower device

  • How fast/slow a device can be interfaced?

  • tDALDI is 0 to 90ns

  • But this is FROM memory

Lecture 12 - Interfacing Devices


Parameters

Parameters

  • Read cycle parameters

Lecture 12 - Interfacing Devices


Memory timing

Memory timing

  • Must consider timing of memory device

Lecture 12 - Interfacing Devices


Memory pinout of the 6116 static ram

Memory Pinout of the 6116 static RAM

Lecture 12 - Interfacing Devices


Items of note

Items of note

  • Chip is 2K x 8-bit

  • Data word is a byte

  • Must use LDS* and UDS* when configuring memory with the device

  • In general memory chips are 1-bit, 1-byte, or 1-word in width of the data interface.

Lecture 12 - Interfacing Devices


Connecting up the 6116

Connecting up the 6116

Lecture 12 - Interfacing Devices


Interfacing devices to the 68000

  • Ended here on Monday 11/15

Lecture 12 - Interfacing Devices


Combined 68000 6116 timing

Combined 68000, 6116 timing

Lecture 12 - Interfacing Devices


The write cycle

The write cycle

  • Timing of processor and memory device must work for both reading device and writing device

  • It is possible that timing will work for read but not for write for a given device

  • I/O devices may be such that they are only written to or read from

  • Example: On modern motherboards you may need matched DIMMs in pairs for the faster memory access speeds. (4GB Dual Channel DDR3 RAM – PC12800, 1600MHz (2x2048MB)

Lecture 12 - Interfacing Devices


Write cycle timing

Write cycle timing

Lecture 12 - Interfacing Devices


Write cycle parameters

Write cycle parameters

Lecture 12 - Interfacing Devices


Write cycle timing of 6116

Write cycle timing of 6116

Lecture 12 - Interfacing Devices


68000 6116 combination for write

68000-6116 combination for write

Lecture 12 - Interfacing Devices


General notes

General notes

  • Can use memory or I/O devices that are designed for the processor family

    • Easy generation and use of interface pins such as CS*, AS*, DTACK*, etc.

    • Little glue logic (sometimes almost none)

  • Use of generic memory and I/O devices

    • May need a fair amount of glue logic and have to generate some signals

    • May be slower than family devices

Lecture 12 - Interfacing Devices


General methodology

General methodology

  • Read cycle timing parameters and specifically those that matter in device interfacing

  • Then the same for write

  • Memory chip timing parameters and how they matches (or don’t) with what we havd

Lecture 12 - Interfacing Devices


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