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Computer Architecture & Organization

Computer Architecture & Organization. Architecture  attributes visible to the programmer. Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques, etc. e.g. Is there a multiply instruction? Control signals, interfaces, memory technology, etc.

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Computer Architecture & Organization

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  1. Computer Architecture & Organization Architecture attributes visible to the programmer • Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques, etc. • e.g. Is there a multiply instruction? • Control signals, interfaces, memory technology, etc. • e.g. Is there a hardware multiply unit or is it done by repeated addition? Organization how features are implemented SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  2. What Should I already know re Computer Arch & Org ? “Black Box” ! connected devices Peripherals communication links keyboard computer mouse network . . . . . . display telephone cable disk / optical wireless speakers printer other ? other ? SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  3. Function & Structure ITBB • SYSC 2001 will look inside the black box ! • peripherals and commn links are outside black box Will construct various models of ITBB components: • Function the operation of individual components as parts of the structure • Structure how components relate to each other SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  4. IMPORTANT SLIDE ! Function • ALL computer functions are: • Data PROCESSING • Data STORAGE • Data MOVEMENT • CONTROL • NOTHING ELSE! Data = Information Coordinates How Information is Used SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  5. Functional view of Black Box Operating Environment source/sink for information connections to peripherals and commn links MOVEMENT ITBB CONTROL PROCESSING STORAGE SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  6. Operations (1) Data movement e.g. copy a file between disks SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  7. Operations (2) Storage e.g. load a text file for editing SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  8. Operation (3) Processing from/to storage e.g. compute an intermediate result from some operands & save for later use SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  9. Operation (4)Processing from storage to I/O e.g. compute and display a result from some operands SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  10. Structure - Top Level ITBB More Black Boxes ITBB! Peripherals Computer Input Output Computer Central Processing Unit Systems Interconnection Communication lines Main Memory What about Function? SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  11. Structure - The CPU CPU Arithmetic and Logic Unit Computer Registers I/O System Bus CPU Internal CPU Interconnection Memory Drilling Down I(ITBB)! Control Unit What about Function? SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  12. Structure - The Control Unit Too deep for SYSC 2001 Control Unit CPU Sequencing Logic ALU Control Unit Internal Bus Control Unit Registers and Decoders Registers Control Memory What about Function? SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  13. Brief History of Computer Evolution Two phases: • before VLSI 1945 – 1978 • ENIAC • IAS • IBM • PDP-8 • VLSI 1978  present day • microprocessors ! VLSI = Very Large Scale Integration see text discussion SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  14. Cell 234 M Growth in CPU Transistor Count Pentium Evolution PowerPC Evolution Moore’s Law SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  15. Speeding Up the Processor • Pipelining • On board cache • On board L1 & L2 cache • Branch prediction • Data flow analysis • Speculative execution we’ll see some of these as the course progresses SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  16. But Performance Mismatch! • Processor speed increased • Memory capacity increased • Memory speed lags behind (and increasing slower than) processor speed SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  17. DRAM and Processor Characteristics SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

  18. Some Solutions • Increase number of bits retrieved at one time • Make DRAM “wider” rather than “deeper” • Change DRAM interface • Cache • Reduce frequency of memory access • More complex cache, and cache on chip • Increase interconnection bandwidth • High speed buses • Hierarchy of buses SYSC 2001 - Fall 2009. SYSC2001-Ch1.ppt

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