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Fault Tolerance and Online Testability of Reversible Logic

Fault Tolerance and Online Testability of Reversible Logic. Presented by Kaynat Quayyum Roll: RH-209 Farzana Sharmin Farah Roll: RH-234. Department of Computer Science & Engineering University of Dhaka. Overview. Fault Tolerant System Reversible Fault Tolerant Gates

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Fault Tolerance and Online Testability of Reversible Logic

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  1. Fault Tolerance and Online Testability of Reversible Logic Presented by KaynatQuayyum Roll: RH-209 FarzanaSharmin Farah Roll: RH-234 Department of Computer Science & Engineering University of Dhaka

  2. Overview Fault Tolerant System Reversible Fault Tolerant Gates Online Testability Gates with Built-in Testability Online Testable Block Railchecker Online Testable Circuit Constructing online testable 2 to 4 decoder References

  3. Fault Tolerant System Property that enables a system to continue operating properly in the event of the failure. No single point of failure Fault isolation to the failing component Fault containment to prevent propagation of the failure Availability of reversion modes

  4. Reversible Fault Tolerant Gates (1/2) Solve the problem of bit error Reversible Parity preserving

  5. Reversible Fault Tolerant Gates (2/2) A A A P = A P = A P = A Fredkin Gate B B B Q = A’B AC Q = A B Q = B’C AC’ NFT F2G C C C R = A C R = A’C AB R = BC AC’ (b) New fault tolerant gate (a) Feynman double-gate (c) Fredkin gate Figure 11: Fault Tolerant Gates

  6. A B C P Q R 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 Fredkin Gate (1/2) • Fault tolerant Parity A P = A Even Fredkin Gate 1 Q = A’ Odd 0 Odd 1 Q = A’ Even 0 R = A Odd Even Even Figure 11: Fault tolerant Fredkin Gate Odd

  7. Fredkin Gate (2/2) Universal gate Can be used as swapping gate 0 1 P = 0 P = 1 Fredkin Gate Fredkin Gate B B Q = B Q = C C C R = C R = B Figure 12: Fredkin Gate as swapping gates

  8. Online Testability Ability of a circuit to test a reversible block at computation time. Testing in implementation phase saves time.

  9. Gates with Built-in Testability Online testable gate proposed by Dilip P. Vasudevan. Used in pairs to make a testable block. R2 Gate Gate R D A E B R P R1 Gate F C

  10. Online Testable Block A X B R 1 Gate Y R 2 Gate Z C Q 0 S 1 A X B Y R 2 Gate TB C Z 0 Q 1 S If Q = S’ then R1 is fault free

  11. Railchecker (1/4) Used for the purpose of checking the output of online testable block. First railchecker circuit proposed using R3 gate. A B R 3 Gate C 11

  12. Railchecker (2/4) x1 • Error checking function: • e1=x0y1+y0x1 • e2=x0x1+y0y1 • x0/y0 and x1/y1 are compliment of each other. So, for fault free circuit e1=e2’ R3 R3 e2 1 1 y0 x0 y0 R3 R3 1 1 y1 R3 x1 R3 e1 1 1 Railchecker using R3

  13. Railchecker (3/4) In Improved railchecker (IRC) output D did the same task as e1 and e2 for pair railchecker G X0 Feynman Gate X1 G Fredkin Gate 1 G C=0

  14. Railchecker (4/4) a b TB R1+R2 1 0 1 TB R1+R2 1 0 1 c d TB R1+R2 1 0 1 e IRC IRC IRC 0

  15. Constructing Online Testable Circuit Step1:Convert each reversible gate to deduced reversible gate Step 2:Construction of testable reversible cell Step 3: Construct Testable cell TC when we have N TRC

  16. Constructing Online Testable Circuit… Step1:Convert each reversible gate to deduced reversible gate O1 I1 I1 O1 O2 I2 I2 O2 Deduced reversible gate (DRG) O3 I3 I3 O3 N*N reversible gate In-1 On-1 On-1 In-1 In On Pout On In Pin Input vector: I = [I1 , I2, .. In] Output Vector: O = [O1, O2, … On] where

  17. DRGa DRGb TRC Constructing Online Testable Circuit… Step 2:Construction of testable reversible cell I1 O1 I1 O1 O2 I2 O2 I2 I3 O3 I3 O3 On-1 In-1 In-1 On-1 On In In On Pob Pia Pia Poa Pib Pob Pib Pob Case 1: if Pia =Pib and if Poa≠pob then one of the output of DRGa or DRGb is faulty

  18. DRGa DRGb TRC Constructing Online Testable Circuit… Step 2:Construction of testable reversible cell I1 O1 I1 O1 O2 I2 O2 I2 I3 O3 I3 O3 On-1 In-1 In-1 On-1 On In In On Pob Pia Pia Poa Pib Pob Pib Pob Case 2: if Pia ≠ Pib and if Poa=pob then one of the output of DRGa or DRGb is faulty

  19. TC Constructing Online Testable Circuit… Step 3: Construct Testable cell TC when we have N TRC Here,  Qoai = poai  Qobi = pobi  E    = T  (if there is no error) Q′oa1 p′oa1 p′ob1 Q′ob1 p′oa2 Q′oa2 p′ob2 Q′ob2 Q′oan p′oan Q′obn p′obn E=0 T Case 1 :If there is a any single bit error in any of the TRC then T=1 Because we provide E = 0 and poai = pobi

  20. Constructing online testable 2 to 4 decoder

  21. Constructing online testable 2 to 4 decoder…

  22. Constructing online testable 2 to 4 decoder…

  23. Constructing online testable 2 to 4 decoder… if T = 1 then there is a Error

  24. Constructing online testable 2 to 4 decoder… Not same, TRC1 is Faulty if T = 1 then there is a Error

  25. Constructing online testable 2 to 4 decoder… Not same, TRC2 is Faulty if T = 1 then there is a Error

  26. Constructing online testable 2 to 4 decoder… Not same, TRC3 is Faulty if T = 1 then there is a Error

  27. References • Behrooz Parhami, “Fault-Tolerant Reversible Circuits” • Dilip P. Vasudevan, “Reversible-Logic DesignWith Online Testability”. • Sk Noor Mohammad, “Constructing Online Testable Circuits Using Reversible Logic”. • N.M. Nayeem and J. E. Rice, “A simple Approach for Designing Online Testable Reversible Circuits”

  28. Thank you

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