Sar atr hour for the slaac fall 99 retreat
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SAR ATR Hour for the SLAAC Fall ‘99 Retreat. Intro/Module Performance Goals: Brian Bray FOA: Scott Hemmert SLD: Steve Crago CDI: Mike Wirthlin Wrap-up (Good/Bad/Future): Brian Bray. Current Challenge Problem Modules. FOA (Focus of Attention)

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SAR ATR Hour for the SLAAC Fall ‘99 Retreat

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Sar atr hour for the slaac fall 99 retreat

SAR ATR Hourfor the SLAAC Fall ‘99 Retreat

Intro/Module Performance Goals: Brian Bray

FOA: Scott Hemmert

SLD: Steve Crago

CDI: Mike Wirthlin

Wrap-up (Good/Bad/Future): Brian Bray


Current challenge problem modules

Current Challenge Problem Modules

  • FOA (Focus of Attention)

    • adaptive rank order quantization and multi-level morphology

    • quad uP:~2 Mpixels/secACS goal: ~10 Mpixels/sec*

  • SLD (Second Level Detection)

    • for in-the-clear scenarios

    • adaptive attenuation estimation with binary template matching

    • quad uP: ~16000 templates/secACS goal: ~80000 templates/sec

  • CDI (Contamination Distribution Indexer)

    • for camouflage, concealment and deception (CC&D) scenarios

    • epsilon-contaminated mixtures model (~10X more compute intensive than SLD)

    • initial ACS goal is just the 2X not the 1X templates (90% of compute)

    • quad uP: ~1600 templates/sec Inital ACS goal: ~16000 templates/sec End ACS goal: (2X and 1X templates at ~80000 templates/sec)

*Mpixel in downsampled space

microprocessor = PowerPC 750 @ 400Mhz


The good

The Good

  • ACS CDI Performance

  • JHDL

  • BYU students and faculty

  • Virtex parts

    • on-chip memory

    • large amounts of logic


The bad

The Bad

  • We are behind

  • Need an embedded Virtex based ACS board

  • ACS parts with large penalty for large precision and FP operations

  • What is the third generation ACS part?


The future as i see it

The Future (As I See It)

  • Bigger second generation ACS parts and better tools will come

    • third generation will not be here in near term

      • what will it be???

        • Virtex-like with RISC core, I$, D$ and DRAM interface?

        • Will it be an improvement to compute tasks or just system on a chip applications

  • PCI accelerator cards with multiprocessor workstation based groundstations

    • will reduce the need for embedded VME hardware

    • Annapolis Microsystems PCI

      • WildSTAR is a significant improvement over WildForce

    • SLAAC PCI?

      • When compared to the WildSTAR, what design features can a SLAAC PCI Virtex board provide to overcome not being COTS and available now?

  • Daughtercards for embedded VME multicomputers

    • CSPI, Mercury

      • many Mercury only shops for embedded VME multicomputers


Mercury compatible acs node

Race Series

PowerPC

CN ASIC

Race Series

PowerPC

CN ASIC

Race Series

PowerPC

CN ASIC

SDRAM

SDRAM

SDRAM

Virtex

Virtex

Virtex

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

PowerPC

PowerPC

L2$

L2$

Mercury Compatible ACS Node

Can SLAAC get access

to these chips and

enough info to write

SW drivers?

Mercury’s PPC Daughtercard

ACS Daughtercard

Can this bus be run

at a lower clock rate

than 83.3Mhz?

CLK Gen

Boot EEPROM

How do others go

about designing

Mercury compatible

daughtercards?

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