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EE434 ASIC & Digital Systems

EE434 ASIC & Digital Systems. Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu. Digital Design with VHDL. Lecture 12. Introduction. VHDL – VHSIC Hardware Description Language Describes function, behavior, inputs, outputs of a Digital System

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EE434 ASIC & Digital Systems

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  1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

  2. Digital Design with VHDL Lecture 12

  3. Introduction • VHDL – VHSIC Hardware Description Language • Describes function, behavior, inputs, outputs of a Digital System • Copes with increasing complexity • Describes a digital system rather than a procedure • Different from other (software) programming languages

  4. Advantages of HDL • Verification of functionality at the early stage • Design Automation • VHDL to gate level realization • Reduction in circuit design time • Technology independent methodology

  5. Hardware Model

  6. Entity • Describes Inputs and outputs of a design entity add4 isport ( a, b: in std_logic_vector (3 downto 0); c_I: in std_logic; sum:out std_logic_vector (3 downto 0); c_o: out std_logic);

  7. Port Modes • Portsare signals that flow into or out of the design entity • The direction of the flow is called the mode

  8. Types of Ports • Data Types • boolean, bit, bit_Vector, integer • Types for synthesis • std_logic, std_ulogic • Proper library needed library ieee; use ieee.std_logic_1164.all; entity add4 isport ( a, b: in std_logic_vector (3 downto 0); c_i: in std_logic; sum:out std_logic_vector (3 downto 0); c_o: out std_logic);

  9. Architecture • Determines function of an entity Behavioral Design Styles Dataflow Structural Any Combination of above

  10. Behavioral Description • Algorithmic way of description • Gate level implementation is hidden architecture behavioral of eqcomp4 is begin comp: process (a, b) begin if a=b then equals <=‘1’; else equals <=‘0’; end if; end process comp; end behavioral;

  11. Dataflow Description architecture dataflow of eqcomp4 is begin equals<=‘1’ when (a=b) else ‘0’; end dataflow • Specifies how data will be transferred from signal to signal and input to output without the use of sequential statements • Concurrent signal assignment statements

  12. Structural Descriptions • VHDL netlists • Components are instantiated and connected together with signals architecture struct of eqcomp4 is signal x:std_logic_vector (3 downto 0); begin u0: xnor2 port map (a(0),b(0),x(0)); u1: xnor2 port map (a(1),b(1),x(1)); u2: xnor2 port map (a(2),b(2),x(2)); u3: xnor2 port map (a(3),b(3),x(3)); u4: and4 port map (x(0),x(1),x(2),x(3),equals); end struct;

  13. Process • Contain sequential statements that define algorithms • Executed when one of the signals in the sensitivity list has an event proc2: process begin x<=a and b and c; wait on a,b,c; end process proc2; proc1: process (a,b,c) begin x<=a and b and c; end process proc1; Be careful about incomplete sensitivity list.

  14. Data Objects • Constants : Holds a value that cannot be changed within the design description constant width: integer:=8; • The identifier width may be used several times in the code. • Signals : represent wires, used to interconnect components Signal x in the example of structural description

  15. Data Objects (Cont’d) • Variables : used in processes and subprograms architecture example of and8 is begin my_and: process (a_bus) variable tmp: bit; begin tmp:=‘1’; for i in 7 downto 0 loop tmp:= a_bus(i) and tmp; end loop; x<=tmp; end process my_and; end example; Note: Variable does not represent wires like signals

  16. library ieee; use ieee.std_logic_1164.all; entity sig_var is port( d1, d2, d3: in std_logic; res1, res2: out std_logic); end sig_var; architecture behv of sig_var is signal sig_s1: std_logic; begin proc1: process(d1,d2,d3) variable var_s1: std_logic; begin var_s1 := d1 and d2; res1 <= var_s1 xor d3; end process proc1; proc2: process(d1,d2,d3) begin sig_s1 <= d1 and d2; res2 <= sig_s1 xor d3; end process proc2; end behv;

  17. Data Types • Enumeration Types – A list of values that an object of that type may hold. Often used in state machines. type states is (idle, preamble, data, jam) • A signal can be declared to be of the enumeration type signalcurrent_state : states; typeboolean is (false, true); type bit is (‘0’, ‘1’);

  18. Data Types (Cont’d) • Array Types: Multiple elements of the same type type byte is array (7 downto 0) of bit ; type arr32 is array(0 to 31) of std_logic_vector(31 downto 0); Constrained array type Bit_Vector is array (integer range <>) of bit ; Unconstrained array

  19. Data Types (Cont’d) • Subtype is a type with a constraint • Used to define a base type with a constraint subtype byte is bit_vector (7 downto 0); signal byte1, byte2: byte;

  20. Combinational Logic • Concurrent statements • Boolean equations • Selective signal-assignment (with-select-when) • Conditional signal assignment (when-else) • Sequential statements • If-then-else • Case-when

  21. Boolean Operations entity my_design is port ( mem_op, io_op: in bit; read, write: in bit; memr, memw: out bit; io_rd, io_wr: out bit); end my design; architecture control of my_design is begin memw <= mem_op and write; memr <= mem_op and read; io_wr <= io_op and write; io_rd <= io_op and read; end control; • Logical operators do not have an order of preference • Parentheses are required in multilevel logic equations

  22. with-select-when library ieee; use ieee.std_logic_1164.all; entity mux is port ( a, b, c, d: in std_logic_vector (3 downto 0); s: in std_logic_vector (1 downto 0); x: out std_logic_vector (3 downto 0)); end mux; architecture archmux of mux is begin with s select x<= a when “00”, b when “01”, c when “10”, d when others; end archmux; Selective signal assignment

  23. when-else • Conditional signal assignment • Can specify any simple expression architecture archmux of mux is begin x<= a when (s=“00”) else b when (s=“01”) else c when (s=“10”) else d; end archmux; Stream <= “0000” when (state=idle and start=‘0’) else “0001” when (state=idle and start =‘1’) else …………

  24. Sequential Statementsif .. then .. else Contained in a process, function or procedure Similar2: process (addr) begin if addr > x”0F” then step<= ‘1’; else step <= ‘0’; end if; end process; Similar1: process (addr) begin step<=‘0’; if addr > x”0F” then step<= ‘1’; end if; end process; Not_Similar: process (addr) begin if addr > x”0F” then step<= ‘1’; end if; end process; Implicit Memory ‘X’ propagation

  25. case-when Equivalent to with-select-when statement architecture design of test_case is begin process (address) begin case address is when “001” => decode <= X”11”; when “111” => decode <= X”42”; when “010” => decode <= X “44”; when “101” => decode <= X”88”; when others => decode <= X”00”; end case; end process;

  26. Invalid case statements signal VALUE: INTEGER range 0 to 15; signal OUT_1: BIT; case VALUE is -- Must have at least one when end case; -- clause case VALUE is -- Values 2 to 15 are not when 0 => -- covered by choices OUT_1 <= ’1’; when 1 => OUT_1 <= ’0’; end case; case VALUE is -- Choices 5 to 10 overlap when 0 to 10 => OUT_1 <= ’1’; when 5 to 15 => OUT_1 <= ’0’; end case;

  27. Loop A loop statement repeatedly executes a sequence of statements. variable A, B: BIT_VECTOR(1 to 3); -- First fragment is a loop statement for I in 1 to 3 loop A(I) <= B(I); end loop; -- Second fragment is three equivalent statements A(1) <= B(1); A(2) <= B(2); A(3) <= B(3); variable A, B: BIT_VECTOR(1 to 10); . . . for I in A’rangeloop A(I) := not B(I); end loop;

  28. exit signal A, B: BIT_VECTOR(1 downto 0); signal A_LESS_THAN_B: Boolean; . . . A_LESS_THAN_B <= FALSE; for I in 1 downto 0 loop if (A(I) = ’1’ and B(I) = ’0’) then A_LESS_THAN_B <= FALSE; exit; elsif (A(I) = ’0’ and B(I) = ’1’) then A_LESS_THAN_B <= TRUE; exit; else null; -- Continue comparing end if; end loop;

  29. Synchronous logic entity dff_logic is port ( d, clk : in std_logic; q: out std_logic); end dff_logic; architecture example of dff_logic is begin process (clk) begin if (clk’eventand clk = ‘1’) then q<=d; end if; end process; end example; architecture example of dff_logic is begin process (clk) begin if rising_edge (clk)then q<=d; end if; end process; end example;

  30. Resets architecture rexample of dff_logic is begin process (clk, reset) begin if rising_edge (clk) then if reset = ‘1’ then q <= ‘0’; else q <= d; end if; end if; end process; end rexample; architecture rexample of dff_logic is begin process (clk, reset) begin if reset = ‘1’ then q <= ‘0’; elsif rising_edge (clk) then q <= d; end if; end process; end rexample; Asynchronous reset Synchronous reset

  31. Asynchronous Reset and Preset process (asyn_reset, asyn_preset, clk) begin if asyn_reset = ‘1’ then q <= (others => ‘0’); elsif asyn_preset = ‘1’ then q <= (others => ‘1’); elsif clk’event and clk = ‘1’ then q <= data; end if; end process;

  32. Tri-state Buffers process (oe, cnt) begin if oe = ‘0’ then cnt_out <= (others => ‘z’); else cnt_out <= cnt; end if; end process; cnt_out <= (others => ‘z’) when oe= ‘o’ else cnt; collision <= (enable and load) when oe = ‘1’ else ‘z’;

  33. Latches process (GATE, DATA) begin if (GATE = ’1’) then Q <= DATA; end if; endprocess; if (PHI = ’1’) then TEMP <= A; else TEMP <= ’0’; end if; if (PHI = ’1’) then TEMP <= A; end if; Inferred Latch

  34. Component Instantiation The component instantiation statement instantiates and connects components to form a netlist (structural) description of a design. U5: or2 port map (O => n6, I1 => n3, I2 => n1); -- Named association U5: or2 port map (n3, n1, n6); --- Positional association Note: When you use positional association, the instantiated port expressions (signals) must be in the same order as the declared ports.

  35. For-Generate For a 32 bit tri-state bus instantiating the component 32 times is cumbersome U0: threestate port map (cnt (0), oe, cnt_out (0)); gen_label: for i in 0 to 31 generate inst_label:threestate port map (value (i), read, value_out(i)); end generate; A generate scheme is implemented in the concurrent-statement portion of an architecture

  36. Subprograms • Algorithms that are meant to be used more than once in a design • Procedures and functions • A procedure has no return value, but can return information to its caller by changing the values of parameters. • A function has a single value that it returns to the caller, but it cannot change the value of its parameters. Declaration Subprogram Body The syntax of a procedure declaration is procedureproc_name [ ( parameter_declarations ) ] ; The syntax of a function declaration is functionfunc_name [ ( parameter_declarations ) ] returntype_name ;

  37. Function Bit_vector to integer function bv2i (bv: bit_vector) return integer is variable result, abit : integer :=0; variable count : integer := 0; begin --------bv2i bits : for i in bv’low to bv’high loop abit :=0; if ((bv(i) = ‘1’)) then abit := 2**(i-bv’low); end if; result := result + abit; count := count+1; exit bits when count = 32; -----32 bits max end loop bits; return (result); end bv2i;

  38. Packages A package is a design unit that can be used to make its type, component, function, and other declarations visible to design units other than itself. std_logic_1164package defines data types std_logicand std_logic_vector

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