COMP541 Memories - I

1. COMP541Memories - I Montek Singh Oct {8, 15}, 2014

2. Topics • Lab 8 • Briefly discuss RAM specification in Verilog • Overview of Memory Types • Read-Only Memory (ROM): PROMs, FLASH, etc. • Random-Access Memory (RAM) • Static today • Dynamic next

3. Verilog for RAM (Lab 8) module ram_module #( parameter Abits = 4, // Number of bits in address parameter Dbits = 4, // Number of bits in data parameter Nloc = 16 // Number of memory locations )( input clock, input wr, // WriteEnable: if wr==1, data is written into mem input [Abits-1 : 0] addr, // Address for specifying location input [Dbits-1 : 0] din, // Data for writing (if wr==1) output [Dbits-1 : 0] dout// Data read from memory (all the time) ); reg [Dbits-1 : 0] mem[Nloc-1 : 0]; // The actual registers where data is stored // Memory write: only when wr==1 and clock tick always @(posedge clock) if(wr) mem[addr] <= din; assign dout = mem[addr]; // Memory read all the time, no clock involved endmodule

4. Types of Memory • Many dimensions • Read Only vs. Read/Write (or write seldom) • Volatile vs. Non-Volatile • Requires refresh or not • Look at ROM first to examine interface

5. Non-Volatile Memory Technologies • Mask (old)  ROM • read-only memory • Fuses (old)  PROM • programmable read-only memory • Erasable  EPROM • erasable programmable read-only memory • Electrically erasable  EEPROM • electrically-erasable programmable read-only memory • today called FLASH! • used everywhere!

6. Details of ROM • Memory that is permanent • k address lines • 2k items • n bits

7. Notional View of Internals

8. Programmed Truth Table

9. Resulting Programming

10. Mask ROMs • Oldest technology • Originally “mask” used as last step in manufacturing • Specify metal layer (connections) • Used for volume applications • Long turnaround • Used for applications such as embedded systems and, in the old days, boot ROM • but cheap to mass produce!

11. Programmable ROM (PROM) • Early ones had fusible links • High voltage would blow out links • Fast to program • Single use

12. UV EPROM • Erasable PROM • Common technologies used UV light to erase complete device • Took about 10 minutes • Holds state as charge in very well insulated areas of the chip • Nonvolatile for several (10?) years

13. EEPROM • Electrically Erasable PROM • Similar technology to UV EPROM • Erased in blocks by higher voltage • Programming is slower than reading • Today’s flavor is called “flash memory” • Digital cameras, MP3 players, BIOS • Limited life • Some support individual word write, some block • Our boards have it: • A flash memory chip on our Nexys boards • Has a “boot block” that is carefully protected • We will learn to use it in upcoming labs

14. How Flash Works • Special transistor with floating gate • This is part of device surrounded by insulation • So charge placed there can stay for years • Aside: some newer devices store multiple bits of info in a cell • Interested in this? If so, we can cover in more detail w/ transistors

15. Read/Write Memories • Flash is obviously writeable • But not meant to be written rapidly (say at CPU rates) • And often writing must be by entire blocks (disk replacement) • For frequent writing, use RAM

16. Random Access Memories • So called because it takes same amount of time to address any particular location • Not entirely true for modern DRAMs, but somewhat true… • First look at asynchronous static RAM • reading and writingtypically controlled by “handshakes” • clock may still be present, but actions controlled by handshake signals

17. Simple View of RAM • Typical parameters: • some word size n • some capacity 2k • k bits of address line • Need a line to specify reading or writing • typically only one wire needed • sometimes two separate ones

18. Example: 1K x 16 memory • RAM comes in variety of sizes • from 1-bit wide • main issue is no. of pins available on chip • Memory size often specified in bytes • This would be 2KB memory • 10 address lines (=1K locations) • 16 data lines (=2 bytes/location)

19. Writing • Sequence of steps • Set up address lines • Set up data lines • Activate write line (e.g., maybe a positive edge)

20. Reading • Steps • Setup address lines • Activate read line • Data available soon • for asynchronous memory: after simply a specified amount of time • for synchronous memory: after a clock edge

21. Chip Select • Enable: • Usually a line to enable the chip • Why?

22. Timing: Writing

23. Timing: Reading

24. Static vs. Dynamic RAM • Different internal implementations: SRAM vs. DRAM • DRAM: • DRAM stores charge in capacitor • Disappears after short period of time • Must be refreshed • Small size • Higher storage density  larger capacities • SRAM: • SRAM easier to use • Uses transistors (think of it as latch) • Faster • More expensive per bit • Smaller sizes

25. Structure of SRAM • Internally, each bit stored in a “latch” • One memory cell per bit • Cell consists of a few transistors • Not really a latch made of NANDs/NORs, but logically equivalent • Behaves like an SR latch • Control logic • also need extra logic around the latch to make it work like a memory cell

26. Structure of SRAM • Several optimized circuits often used • replace a full-fledged SR latch with something simpler, smaller, faster… • Not really a latch made of NANDs/NORs, but logically equivalent • Behaves like an SR latch • e.g., a simpler 6-transistor memory cell • wordline Select • (bitline, bitline’)  (B, B’) as well as (C, C’)

27. Example: A Simple Organization • Note: • In reality, more complex • Only one word-line is “on” at a time

28. Zoom in: A single bit slice • Operation: • Cells connected to form 1 bit position (column) • Word Select enables one latch from address lines • only this cell is writable • only this cell is read • B (and B’) set by: • Read/Write’ • Data In • Bit Select

29. Let’s look at a single bit cell Example: Z 0 Z 1

30. Bit Slices and Modules • Entire column of cells • called a bit slice • basically a 1-bit wide memory! • Module • module refers to a single chip of memory • 1-bit wide memory chips are quite common!

31. Inside an SRAM Bit Cell • Actual implementation does not use a real SR latch! • a tinier approximation is used • logically behaves very much like an SR latch • but much smaller and faster!

32. 16 X 1 RAM “Chip” • Now shows address decoder • selects appropriate location

33. Row/Column Layout • For larger RAMs: • decoder becomes pretty big • also run into chip layout issues • Typically: • larger memories use “2D”matrix layout • see next slide

34. 16 X 1 RAM as 4 X 4 Array • Two decoders • Row • Column • Address just broken up • Not visible from outside on SRAMs

35. Not the same as 8 X 2 RAM! • Minor change in logic and pins • Spot the difference!

36. Spot the difference!

37. Realistic Sizes • Example: 256Kb memory organized 32K X 8 • Single-column layout would need 15-bit decoder with 32K outputs! • Better organization: • A 2D (i.e., square) layout with: • 9-bit row and 6-bit column decoders

38. SRAM Performance • Latency and Throughput important • Current ones have cycle times in low nanoseconds • say 1-2ns(top-end ones even lower) • Used as cache (typically on-chip or off-chip secondary cache) • Sizes up to 8Mbit or so for fast chips • Expensive ones can go a bit bigger • Energy/power • SRAMs also better for low power vs. DRAMs

39. Wider Memory • What if you don’t have enough bit width? • use multiple chips and side-by-side

40. Larger/Wider Memories • Made up from sets of chips • Consider a 64K by 8 RAM • our building block

41. Larger • Let’s build a larger memory • 256K X 8 • Decoder for high-order 2 bits • Selects chip • Look at selection logic • Address ranges • Tri-state outputs

42. Summary • Today we looked at: • Quick look at non-volatile memory • Static RAM • Next topic: • Dynamic RAM • Complex, largest, cheap • Much more design effort to use • Talk about memories for lab