Array Synthesis in SystemC Hardware Compilation

1. Array Synthesis in SystemC Hardware Compilation Authors: J. Ditmar and S. McKeever Oxford University Computing Laboratory, UK Conference: Field Programmable Logic and Applications (FPL), 2007 Presenter: Tareq Hasan Khan ID: 11083577 ECE, U of S Literature review-1 (EE 800)

2. Outline • Introduction to SystemC and Agility compiler • Mapping SystemC Array • In Register • In FPGA’s RAM • Results • Conclusion

3. SystemC • High level programming language to describe hardware • C++ syntax • Synthesizable subset defined by Open SystemC Initiative (OSCI)

4. Agility SystemC Compiler • Translate SystemC program to HDL language (VHDL, Verilog, RTL SystemC) • Agility accepts most C++ constructs, such as: • conditional statements — if, switch • loop statements — while, do...while, for • control flow — break, continue, return

5. Agility Design Flow

6. Outline • Introduction to SystemC and Agility compiler • Mapping SystemC Array • In Register • In FPGA’s RAM • Results • Conclusion

7. Mapping SystemC Array • SystemC Array Synthesis • Registers using general purpose logic • RAM blocks of modern FPGA • Constrain • SystemC arrays offer parallel access to elements • SystemC arrays are accessed in one cycle • SystemC arrays have write-before-read semantics “Semantics of SystemC array must be preserved after synthesis “

8. Outline • Introduction to SystemC and Agility compiler • Mapping SystemC Array • In Register • In FPGA’s RAM • Results • Conclusion

9. Array Synthesis in Registers for Read Access • Each array element produces a register in hardware • The address decoder translates address x into a bit vector which controls the output multiplexer • The multiplexer selects the output of the particular element that is indexed by x • If an array is read several times, several address decoders and multiplexers are required x y = Array [ x ] Mux y

10. Array Synthesis in Registers for Write Access • The output lines of the address decoder are connected to the write enables of the registers to select in which register to write • If an array is written to multiple times in a same clock cycle, multiplexers are required on the inputs of the registers to select which data to write x Array [ x ] = y y

11. Outline • Introduction to SystemC and Agility compiler • Mapping SystemC Array • In Register • In FPGA’s RAM • Results • Conclusion

12. Array Synthesis in FPGA’s RAM • Modern FPGA contains large amount of RAM • Altera Cyclone II has 512KB of SRAM • A SystemC Array can be accessed by several processes in a single clock cycle • Multi-port RAM is needed • An algorithm is developed to automatically assign memory access to RAM ports

13. Algorithm Constraints and Steps • The algorithm must assign memory access to ports such a way that: • A memory port is never accessed more than once in a clock cycle • The total number of memory ports must be minimized • Steps • Control Flow Graph (CFG) • Access Analysis • Port Assignment

14. Control Flow Graph (CFG) • Codes between two consecutive wait statements executes concurrently in a clock cycle • All possible paths that might be traversed during program execution

15. Access Analysis and Port Assignments R=Read only port W=Write only port RW = Read-Write port One Read only port and Two Write only port required OR One Write only port and One Read-Write port required Each path executes in a single clock cycle

16. Access Analysis Algorithm

17. Outline • Introduction to SystemC and Agility compiler • Mapping SystemC Array • In Register • In FPGA’s RAM • Results • Conclusion

18. Results • Inverse Desecrate Cosine Transform (IDCT) algorithm written in C contains array of 1KB • The design ported from C to SystemC • Used Agility compiler to produce EDIF (Xilinx Virtex-4 FPGA)

19. Conclusion • Mapping of SystemC Array to hardware • In Resister File • Take more logic area • Less performance • In FPGA RAM • A new algorithm to map arrays to memory has been presented • More efficient in terms of logic area

20. Thanks