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Dr. Wissam Hasan Mahdi Alagele

وزارة التعليم العالي والبحث العلمي جامعة الكوفة - كلية التربية – قسم علوم الحاسوب. Digital Logic Design I I I. Chapter 3 Decoder and Encoder . Dr. Wissam Hasan Mahdi Alagele. e-mail:wisam.alageeli@uokufa.edu.iq. http :// edu-clg.kufauniv.com/staff/Mr.Wesam. Decoder definition.

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Dr. Wissam Hasan Mahdi Alagele

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  1. وزارة التعليم العالي والبحث العلمي جامعة الكوفة - كلية التربية – قسم علوم الحاسوب Digital Logic Design III Chapter 3 Decoder and Encoder Dr. WissamHasan Mahdi Alagele e-mail:wisam.alageeli@uokufa.edu.iq http://edu-clg.kufauniv.com/staff/Mr.Wesam

  2. Decoder definition • Decoding is the conversion of an n-bit input code to an m-bit output code with n ≤ m ≤ 2n, such that each valid code work produces a unique output code. • Decoding is performed by a logic circuit called a decoder.

  3. Black box with n input lines and 2n output lines Only one output is a 1 for any given input Binary Decoder Binary Decoder n inputs 2n outputs

  4. A decoder has N inputs 2N outputs A decoder selects one of 2N outputs by decoding the binary value on the N inputs. The decoder generates all of the minterms of the N input variables. Exactly one output will be active for each combination of the inputs. Decoders What does “active” mean?

  5. BinaryDecoder x1 x0 Decoders Only onelamp will turn on • Extract “Information” from the code • Binary Decoder • Example: 2-bit Binary Number 0 1 2 3 1 0 0 0 0 0

  6. n-to-m-line decoders • Circuit has n inputs and m outputs and m ≤ 2n • Start with n=1 and m=2 • This a 1-to-2 Line decoder – exactly one of the output lines will be active.

  7. BinaryDecoder y3 y2 y1 y0 I1 I0 Decoders A decoder when n=2 and m=4 A 2-to-4 line decoder Note that only one output is ever active

  8. Notice they are minterms Truth Table, 3-to-8 Decoder

  9. Schematic

  10. Multi-Level 3-to-8

  11. BinaryDecoder Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 I2 I1 I0 Decoders • 3-to-8 Line Decoder

  12. Enable is a common input to logic functions See it in memories and today’s logic blocks Enable

  13. 2-to-4 with Enable

  14. BinaryDecoder Y3 Y2 Y1 Y0 I1 I0 E Decoders • “Enable” Control

  15. Enable Used for Expansion

  16. BinaryDecoder Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y3 Y2 Y1 Y0 I0 I1 E BinaryDecoder Y3 Y2 Y1 Y0 I0 I1 E Decoders I2 I1 I0 • Expansion

  17. BinaryDecoder BinaryDecoder Y3 Y2 Y1 Y0 Y3 Y2 Y1 Y0 I1 I0 I1 I0 Decoders • Active-High / Active-Low

  18. BinaryDecoder Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 x y z I2 I1 I0 S C Implementation Using Decoders • Each output is a minterm • All minterms are produced • Sum the required minterms Example: Full Adder S(x, y, z) = ∑(1, 2, 4, 7) C(x, y, z) = ∑(3, 5, 6, 7)

  19. BinaryDecoder BinaryDecoder Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 x y z x y z I2 I1 I0 I2 I1 I0 S C S C Implementation Using Decoders

  20. An encoder has 2N inputs N outputs An encoder outputs the binary value of the selected (or active) input. An encoder performs the inverse operation of a decoder. Issues What if more than one input is active? What if no inputs are active? Encoders

  21. x1 x2 x3 1 BinaryEncoder y1 y0 2 3 Encoders Only oneswitch should be activated at a time • Put “Information” into code • Binary Encoder • Example: 4-to-2 Binary Encoder

  22. BinaryEncoder I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 Encoders • Octal-to-Binary Encoder (8-to-3)

  23. 0 2 3 4 5 6 7 1 Encoder / Decoder Pairs BinaryEncoder BinaryDecoder Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 I7 I6 I5 I4 I3 I2 I1 I0 7 6 5 Y2 Y1 Y0 I2 I1 I0 4 3 2 1 0

  24. MUX I0 I1 I2 I3 Y S1 S0 Multiplexers

  25. MUX I0 I1 Y S MUX I0 I1 I2 I3 Y S1 S0 Multiplexers • 2-to-1 MUX • 4-to-1 MUX

  26. MUX I0 I1 MUX Y A3 A2 A1 A0 S MUX I0 I1 Y3 Y2 Y1 Y0 Y S MUX B3 B2 B1 B0 I0 I1 Y S MUX I0 I1 S E Y S Multiplexers • Quad 2-to-1 MUX x3 x2 x1 x0 y3 y2 y1 y0 S

  27. MUX A3 A2 A1 A0 Y3 Y2 Y1 Y0 B3 B2 B1 B0 S E Multiplexers • Quad 2-to-1 MUX Extra Buffers

  28. MUX I0 I1 I2 I3 Y S1 S0 Implementation Using Multiplexers • ExampleF(x, y) = ∑(0, 1, 3) 1 1 0 1 F x y

  29. MUX I0 I1 I2 I3 I4 I5 I6 I7 Y S2 S1 S0 Implementation Using Multiplexers • ExampleF(x, y, z) = ∑(1, 2, 6, 7) 0 1 1 0 0 0 1 1 F x y z

  30. MUX I0 I1 I2 I3 Y S1 S0 Implementation Using Multiplexers • ExampleF(x, y, z) = ∑(1, 2, 6, 7) z F = z F z 0 F = z 1 F = 0 x y F = 1

  31. MUX I0 I1 I2 I3 I4 I5 I6 I7 Y S2 S1 S0 Implementation Using Multiplexers • ExampleF(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15) D F = D D F = D D 0 F = D F 0 F = 0 D F = 0 1 1 F = D F = 1 F = 1 A B C

  32. I0 I1 I2 I3 I4 I5 I6 I7 MUX I0 I1 Y Y S MUX MUX I0 I1 I2 I3 I0 I1 I2 I3 Y Y S1 S0 S1 S0 S2 S1 S0 Multiplexer Expansion • 8-to-1 MUX using Dual 4-to-1 MUX 1 0 0

  33. DeMUX Y3 Y2 Y1 Y0 I S1 S0 DeMultiplexers

  34. 2 4 5 6 7 1 0 3 Multiplexer / DeMultiplexer Pairs MUX DeMUX Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 I7 I6 I5 I4 I3 I2 I1 I0 7 6 5 4 Y I 3 2 1 0 S2 S1 S0 S2 S1 S0 Synchronize x2x1x0 y2 y1 y0

  35. BinaryDecoder Y3 Y2 Y1 Y0 I1 I0 E DeMUX Y3 Y2 Y1 Y0 I S1 S0 DeMultiplexers / Decoders

  36. A Y C Three-State Gates • Tri-State Buffer • Tri-State Inverter A Y C

  37. A C B Three-State Gates A Y C B Not Allowed D Aif C= 1 Bif C= 0 Y=

  38. Three-State Gates I3 I2 Y I1 I0 BinaryDecoder Y3 Y2 Y1 Y0 I1 I0 E S1 S0 E

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