Paul Theo Gonciari*, Bashir Al-Hashimi* and Nicola Nicolici** *University of Southampton, UK

1. Improving Compression Ratio, Area Overhead, and Test Application Time in System-on-a-chip Test Data Compression/Decompression Paul Theo Gonciari*, Bashir Al-Hashimi* and Nicola Nicolici** *University of Southampton, UK **McMaster University, Canada

2. Why Test Data Reduction ? • Exponential increase in volume of test data (ITRS) • 60% of ATE upgrade caused by memory (EETimes) • Solutions • Built-in self-test (BIST) • Test data reduction • Useful • Useless • Useful • Compaction • does not reduce bandwidth • Compression • reduces bandwidth • further reduces test time

3. Overview • Test data compression (TDC) • Environment • Previous work • Variable-length Input Huffman Coding (VIHC) • Compression algorithm • Decompression architecture • Experimental results • Conclusions & Future work

4. Test Data Compression (TDC) • Post ATPG process • Reduces size of test set • Exploits nature of test sets: • Mapping • Reordering • Difference sequence • Exploits nature of patterns: • Length • Type • Requires on-chip decoder ATPG Initial test set Test data compression Compressed test set Test vector database

5. TDC Environment (TDCE) • Compression ratio • Mapping & reordering • Type of input patterns • Length of the pattern • Compression algorithm • Area overhead • Nature of decoder • Type of input pattern • Length of pattern • Test application time (TAT) • Nature of decoder • Length of pattern • Frequency ratio ATE reduced bandwidth on-chip decoder Initial test set CUT

6. TDC – Previous Work • Selective Coding (SC) [Jas et. al – VTS99] • large decoder • parallel decoder • low TAT • Golomb codes [Chandra et. al – TCAD01] • small decoder • serial decoder • large TAT • FDR codes [Chandra et. al – VTS01] • fixed size decoder • serial decoder • large TAT

7. Variable-length Input Huffman Coding • Variable-length Input Huffman Coding (VIHC) • Employs variable-length input patterns • Uses Huffman coding to obtain optimum code • Uses parallel on-chip decoder to reduce TAT • Compression Algorithm • Step 1 - Prepare initial test set • mapping “don’t cares” • reordering • number of 1s in the difference is minimum • minimum run of 0s maximum • Step 2 - Huffman code computation • exploits variable length patterns • Step 3 - Generate decoder information • determines the on-chip decoder

8. m = 4 t = 26 bits t = 16 bits h init cmp t 1 01 0000 0000 0000 0001 0000 001 init t cmp 000 001 1 1 1 011 1 010 1 0 Pattern Occurrence Code L = 1 1 000 0 1 01 0 = L 01 1 001 1 0 0 001 L 001 1 010 = 1 2 = L 0001 1 011 3 1 = 0001 L 0000 4 1 1 4 0000 Dictionary Huffman tree VIHC - Code Computation

9. m = 4 V G t = 26 bits t = 17 bits t = 19 bits h init cmp cmp t init 1 01 0000 0000 0000 0001 0000 1 01 V t cmp 00 011 1 1 1 010 1 00 011 G t cmp 000 001 1 1 1 011 1 000 001 Pattern Occ. Code Run of 0s Golomb code L = 1 2 00 1 000 0 = L 01 2 011 01 001 1 = L 0001 1 010 0000 0000 0000 0001 1 1 1 011 3 = L 0000 4 1 0000 1 1 000 4 VIHC vs. Golomb [TCAD01]

10. Huffman decoder data code special ATE sync data out data in data in FSM clk FSM clock scan clock chip test clock CGU VIHC – Decoder • VIHC parallel on-chip decoder • Huffman decoder • Control and Generation Unit (CGU)

11. Compression Ratio Comparison

12. Area Overhead Comparison

13. Test Application Time Comparison

14. similar improved a r Comparison Overview

15. Conclusion & Future Work • Proposed • New VIHC method • New compression/decompression scheme • Improves all the TDCE parameters • Good compression ratio • Small area overhead • Low test application time • Future work • Reduce synchronization overhead • Exploit core wrapper design for TDC