Computer Architecture Shared Memory MIMD Architectures. Ola Flygt Växjö University http://w3.msi.vxu.se/users/ofl/ Ola.Flygt@msi.vxu.se +46 470 70 86 49. Outline. Multiprocessors Cache memories Interconnection network Shared path Switching networks Arbitration
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Computer ArchitectureShared Memory MIMD Architectures
+46 470 70 86 49
Enable the temporary connection of any two components of a multiprocessor.
The priority loop of the rotating arbiter works similarly to the grant chain of the daisy-chained arbiter.
- unnecessary traffic on interconnection in case of private data and of infrequently used shared data
+ more reliable (error detection and recovery features of the main memory)
- more complex cache controllers
- cache controllers have to accept invalidate command from other cache controllers
E = Exclusive state
M = Modified state
Sc = Shared clean state
Sm = Shared modified state