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National Sun Yat-sen University Embedded System Laboratory. Implementation and Prototyping of a Complex Multi-Project System-on-a-Chip Chun-Ming Huang, Chien -Ming Wu, Chih-Chyau Yang, Wei-De Chien , Shih- Lun Chen,

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Presenter ching hua huang

National Sun Yat-sen University Embedded System Laboratory

Implementation and Prototyping of a Complex Multi-Project System-on-a-Chip

Chun-Ming Huang, Chien-Ming Wu, Chih-ChyauYang, Wei-De Chien, Shih-LunChen,

Chi-Shi Chen, Jiann-JennWang, and Chin-Long WeyNational Chip Implementation Center (CIC), Hsinchu, Taiwan

Department of Electrical Engineering, National Central University, Jhongli, Taiwan

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Presenter :Ching-Hua Huang


Abstract 1
Abstract(1)

  • A silicon prototyping methodology is presented for Multi-Project System-on-a-Chip(MP-SoC)implementation. A multi-projects platform was created for integrating heterogeneous SoCprojects into a single chip. The total silicon prototyping cost of these projects can be greatly reduced by sharing a common platform.

  • To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with ten SoCprojects sharing the common platform. The total silicon area is about 37.97mm2in the TSMC 0.13um CMOS generic logic process technology. Compared with the total chip area 129.39mm2by implementing these projects separately, the results show that there are 91.42mm2 silicon areas reduced by the MP-SoCplatform.


Abstract 2
Abstract(2)

  • In order to verify MP-SoC through silicon prototyping, a system modeling and hardware/ software co-design virtual platform were implemented.

  • A configurable SoC prototyping system, namely CONCORD, is also created as a verification platform for emulating the hardware of MP-SoC before chip being taped-out. The CONCORD system provides higher connection flexibility, modularization, and architecture consistence than conventional FPGA systems.


What’s the problem

4

  • Many projects will be integrated in a SoC, namely MP-SoC.

    • Reduced more area cost by use the MP-SoC.

  • In order to improve the robustness of MP-SoC design and verification

    • A design flow was developed by CIC.


Related work

ARM™

RealView Versatile

[1]

System level integration

[2]

Platform-based design

[other paper reference]

[6]

[3-5]

An automatic SOC

integration platform “STEAC” was used to facilitate MP-SoCtest integration

Resolve the problem of high fabrication cost for SoCdesigns

[Popular methodology]

Integrated a complex system into a single chip

[This paper]

A Novel Methodology for

Multi-Project System-on-a-Chip

[1] Surviving the SoC Revolution: A Guide to PlatformbasedDesigns

[2] Multiprocessor SoC Platforms: A Component-Based Design Approach

[3] A Case Study of the Novel Low-Cost SoC Silicon Prototyping Service for Taiwan Academia

[4] Multi-ProjectSystem-on Chip (MPSoC): A Novel Test Vehicle for SoCSilicon Prototyping

[5] PrSoC: Programmable System-on-Chip (SoC) for Silicon Prototyping

[6] ARM RealView Versatile, ARM

[other paper reference] STEAC: A platform for automatic SOC test

5


Proposed method

  • Virtual Prototyping

    • Asystem modeling and HW/SW co-design virtual platform – ESL design methodology

  • Logical Implementation

    • For IP’s development and verification

  • Rapid Prototyping

    • ARM RealView Versatile

    • A “CONCORD” platform

  • Physical Implementation

    • The MP-SoC chip taped out to the foundry

  • Testing and Measurement

    • Verigy 93000 ATE

    • Customized development board


Virtual prototyping
Virtual Prototyping

Verilog-based IP module

  • The 1’st goal – CoSim

    • All Verilog-based IP modules are packed with TLM interfaces and connected to SystemC-based platform in the simulation environment.

  • The 2’nd goal – Performance analyze

    • These analysis functions help designers to detect the system bottlenecks.

  • Faster simulation speed

    • About 100times than pre-simulation.


Logical implementation
Logical Implementation

Netlist->pre-sim

IP1

HDL coding

Synthesis

DFT/ATPG

Synthesis

IEEE 1500 wrapper

Synthesis

HDL code

Synthesis

DFT/ATPG

IPn

HDL coding

STEAC

STEAC

APR

Netlist->

post-sim

Test patterns

FPGA

  • STEAC: SOC TEST AID CONSOLE

  • Synopsys VIP :SynopsysVerification IP

    • Provide the effective approach to verify circuit

      • It also can build the SoC platform rapidly.

    • Provide the Functional Coverageand Monitoring

      • It can analyze this design whether conform to the specification.


Rapid prototyping two platform
Rapid Prototyping – Two platform

  • ARM™ RealViewVersatile

    • The connection architecture is not enough

      • Support item

        • One core tile sub board

        • One FPGA tile sub board

  • CONCORD

    • The bus architecture is designed into the main board

    • The silicon IPs are designed into the sub boards

      • Support OpenRISC、ARM andLEON3 system


Physical Implementation and Testing

10

  • TSMC 0.13um 1P8M

  • There are two testing environments are used in this MP-SoC.

    • Verigy 93000 ATE

    • Customized development board


Conclusion
Conclusion

10 IPs

=129.39

10 IPs

91.42

=37.97

v

v

v

  • The silicon area can be significantly reduced.

    • Saving approximately 70.6 % silicon area than fabricated individually.

  • A CONCORD platform

    • Emulating the MP-SoChardware before chip taping out.


My comment
My comment

  • This paper is related to my tape-out working

    • Virtual Prototyping

      • Co-Ware

    • Logical Implementation

      • FPGA verification

      • Design compiler, IEEE 1500 wrapper, DFT and ATPG

        • Pre-layout simulation

      • SoC encounter, DRC and LVS check

        • Post-layout simulation

    • Testing and Measurement

      • Verigy 93000 ATE

      • Customized development board

  • It provide the different design approaches

    • STEAC : A platform for automatic SOC test

    • CONCORD : A modulation SoC verification platform


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