html5-img
1 / 9

Silicon Pixel FEM R&D

Silicon Pixel FEM R&D. Basic concept of pixel FEM NA60 readout scheme Schematic readout scheme for PHENIX R&D Program. Three Students working with me over the summer: Sanjee Abeytunge MSI Thesis Fall 2003 Alan Dion FEM readout tests at BNL Dylan Walker at CERN with NA60.

dewei
Download Presentation

Silicon Pixel FEM R&D

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Silicon Pixel FEM R&D Basic concept of pixel FEM NA60 readout scheme Schematic readout scheme for PHENIX R&D Program Three Students working with me over the summer: Sanjee Abeytunge MSI Thesis Fall 2003 Alan Dion FEM readout tests at BNL Dylan Walker at CERN with NA60

  2. Silicon Pixel FEM • Basic assumption: Pixel readout will be similar to ALICE & NA60 readout • Pilot chip • GOL for optical transmission (Glink or cupper) • JTAG slow control • Function of pixel FEM • Multiplex multiple pilot/GOL chips or ladders • Adapt output from pixel ladder to “PHENIX” readout • Readout prototype pixel chips into PHENIX DAQ with existing DCM’s • Option to use existing PHENIX DCM’s (e.g. from MVD) • Other features • Optional zero suppression • Scheme expandable to other detector systems (silicon strips or HBD ..) • Central control board CCB • Slow control ArcNet (or what ever replaces it) to JTAG conversion • Clock distribution • Trigger distribution Axel Drees

  3. ArcNet (slow control) Central Control Board (one for all) GTM (trigger & clock) Present Readout Scheme JTAG, clock clock, trigger Multiple Pilot/GOL per ladder F I F O FPGA F I F O FPGA Silicon Pixel Ladders Piggy back receiver Glink DCM Axel Drees

  4. R&D towards FEM (update from DAQ Meeting 10/2002) • Create programmable data source (NI 5311) • Hardware & Labview software available (S.Abeytunge) • First readout tests (planed for this summer A.Dion) • Simulate pixel data • read through DC FEM (in principle available thanks to L.Hammons) • develop test software • implement zero suppression algorithm • Develop FEM prototpye (Master Thesis S.Abeytunge Fall 2003) • Data collector and Glink data transmission • Adaptable to data source and real pixel chip • Central Control Board prototype (similar board developed for NA60 strip readout by S. Abeytunge, reusable?) • trigger, clock • JTAG • FEM Test readout • two data sources • Obtain “real” data source (D.Walker at CERN over summer) • ALICE single chip board • NA60 multichip interface • Develop control of pixel chip (Fall 2003) • ArcNet JTAG translation • slow control software • HV and LV • Test readout with DC FEM • Readout test with FEM prototype Axel Drees

  5. Programmable Data Source • Based on National Instrument 40 MHz arbitrary waveform generator NI5411 system available • based on PXI bus • 2x16 bit digital (TTL) pattern (two units synchronized) • 40 MHz output (internal and external clock) • 16 Mbyte memory • Multiple data segments released sequentially on internal or external trigger • Labview control program available Software developed and tested by S Abeytunge Axel Drees

  6. Old slides Axel Drees

  7. NA60 pixel read out PCI card & Mezzanine Pixel plane Multichip interface Glink (twisted pair) data, busy, control words 4 pixel chips burst buffer GOL Glink receiver Control bus 16 bit 20 MHz ? 40 MHz clock FPGA Data bus Pilot FPGA JTAG clock,trigger,slow control 32 bit 10 MHz Low voltage “analog pilot” not shown busy trigger burst Glink JTAG connection Zero suppression: replace 0 words by counter Generate busy: count evt received & triggers send Corresponds to PHENIX Pixel ladder hope to receive test chain this year: 1 chip test board + interface PHENIX FEM collects data from multiple pilot chips could do zero suppression PHENIX DCM Axel Drees

  8. DCM: data busy GLink Schematic layout of FEM • 2 kByte data from each pilot • ~32000 16 bit words • multiple pilots deliver data to one FEM • one side max. 20 pilot chips • assume 4 pilots (one ladder) per FEM • 5 FEM per side, 20 in total • Zero suppression on FEM (optional) • light suppression • marker arm/side/pilot/chip • replace empty 16 bit words by word counter • max length ~ raw data length • full suppression • marker arm/side/pilot/chip • only hit pixel rphi (8 bit), z (5 bit) • Busy generated by FEM and transmitted to DCM • transmit with data ala pilot chip? controller for 1 pilot Arcnet Slow control FPGA JTAG GTM: Trigger clock GLink FPGA GLink data collector Axel Drees

  9. Receiver FiFo Receiver FiFo Receiver FiFo Receiver FiFo Receiver FiFo FPGA FPGA FPGA FPGA FPGA (Universal Silicon) FEM readout scheme data bus • 8 kByte data stream from each pilot: • via cable or optical fiber • no zero suppression • 5 pilot chips deliver data to one FEM • 2 (6) FEM’s per arm • 1 (3) for each side • FEM’s suppress zero’s and reformat data • marker word 1 bit arm (16 bit) 1 bit side 2 bit FEM 3 bit pilot 3 bit chip • data word 8 bit for word (r) (16 bit) 5 bit for channel (z) • data volume per FEM (for central collision) • uncompressed 40 kByte • 16 bit per word ~3.3 kByte • 40 marker words (one/chip) • 3300 data words (1% occupancy) FEM Transmitter GLink Axel Drees to DCM

More Related