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COSC 3330/6308 Solutions to First Problem Set

COSC 3330/6308 Solutions to First Problem Set. Jehan-François Pâris September 2012. First problem (I). A program consists of two parts, namely One part is purely sequential and takes 64 s to complete Another part takes 1,024 s when run on a uniprocessor architecture

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COSC 3330/6308 Solutions to First Problem Set

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  1. COSC 3330/6308Solutions toFirst Problem Set Jehan-François PârisSeptember 2012

  2. First problem (I) • A program consists of two parts, namely • One part is purely sequential and takes 64 s to complete • Another part takes 1,024 s when run on a uniprocessor architecture • Can be easily decomposed into two or more parallel tasks • Speedup would be proportional to the number of tasks executing in parallel.

  3. First problem (II) • What would be the speedups that the program would achieve if it was to run on computers with 2, 4, 8, 16, and 32 processors? • What would be the maximum speedup that the program would achieve if it was to run on a computer with an unlimited number of processors?

  4. Answer (I) • Will use Amdahl's law

  5. Answer (II)

  6. Second problem • Simplify the two following logical expressions: • ABC'D' + AB'D' + ACD + CD • (A  BC) (B + A) using both algebra and Karnaugh maps.

  7. First expression (I) • ABC'D' + AB'D' + ACD + CD =ABC'D' + AB'D' + CD =ABC'D' + AB'D' + AB'C'D' + CD =AC'D' + AB'D' + CD

  8. First expression (II) AC'D' + AB'D' +CD

  9. Second expression (I) • (A  BC) (B + A) = (A(BC)' + A'BC) (A + B) =(AB' + AC' + A'BC) (A + B) =AB' + AC' + A'BC + ABC' =AB' +AC' +A'BC

  10. Second expression (II)

  11. Second expression (III) AB' + AC' +A'BC

  12. Second expression (IV) AB' + AC' +A'BC

  13. Third problem • Simplify the expression • (ABC)' (A + DE)' (A BC) (B + E) and convert it to a form that can be represented using a programmable logic array.

  14. Answer (I) • (ABC)' (A + DE)' (A BC) (B + E) • Let us do it in two parts • (ABC)' (A + DE)' =(A' + B' + C')(A'(DE)') =(A' + B' + C')(A'(D' +E') =A'(D' +E') + A'B'(D' +E') +A’C’(D’ +E’) =A'D' +A'E'

  15. Answer (II) • The second part is • (A BC) (B + E) =(A(BC)' + A'BC)(B + E) =(AB' + AC' + A'BC)(B + E) =ABC' + A'BC + AB'E + AC'E + A'BCE

  16. Answer (III) • The product is • (A'D' +A'E')(ABC' + A'BC + AB'E + AC'E + A'BCE) =A'BCD' + A'BCE' + A'BCD'E = A'BCD' + A'BCE' • Sum of products can be represented by a PLA I checked the answer on a spreadsheetwith 25 rows and 14 columns

  17. Fourth problem • Implement the double implication operation: • A  B = AB +A’B’ using only NAND gates.

  18. NAND gates • A nand B = (AB)' = A' + B' • nand (A) nand nand(B) = (A'B')' = A + B • nand(A nand B) = (AB)'' = AB • nand(nand(A) nand nand(B)) =(A' B')'' = A'B'

  19. Answer ((A + B)(A' + B')' =(A + B)' + (A' + B')' = A'B' +AB A+B A B A B A'+B' I started with a solution havingmore NANDs and simplified it

  20. Fifth problem • Build a regular D flip-flop using an R’S’ latch, that is, an RS latch with inverted values for R and S, and as few NOR gates as possible.

  21. NOR gates • A nor B = (A + B)' = A' B' • nor (A) nor nor(B) = (A' + B')' = AB • nor(A nor B) = (A+B)'' = A + B • nor(nor(A) nor nor(B)) =(A' + B')'' = A' + B'

  22. S' Q' Clock R' Q From S'R' latch to D flip-flop • S'R' has three inputs • S' sets latch when S' = 0and clock = 1 • R' resets latch when R' = 0and clock = 1 • D flip-flop • Stores a 1 at clock transition when input is 1 • Stores a 0 at clock transition when input is 0

  23. S Q Clock R Q' D flip-flop using an S-R latch X Clock

  24. S' Q Clock R' Q' D flip-flop using an S'-R' latch X Clock

  25. S' Q R' Q' Clock Introducing NORs X Clock (Clock+Clock')'=ClockClock'

  26. S’ Q Q’ R’ Note • The solution is fairly simple because we assumed that the R'S' latch had a clock entry • Solution for R'S' latch without clock input is more complex

  27. Sixth problem (I) • Build a synchronous sequential circuit with • Two inputs, respectively named P—for plus—and M—for minus • Two outputs respectively named O—for overflow—and U—for underflow

  28. Sixth problem (II) • The transitions are:

  29. Answer • Eight states • Three flip-flops X Y Z • Will consider separately • How P inputs affect X, Y, Z • How M inputs affect X, Y, Z • When counters outputs O and U

  30. How P inputs affect Z

  31. Solution • Z = P'Z + PZ' • Will use a T flip-flop triggered by P

  32. How P inputs affect Y

  33. Solution • Y = P'Y + PYZ' + PY'Z • Will use a T flip-flop triggered by PZ

  34. How P inputs affect X

  35. Solution • X = P'X + PXY' + PXZ' + PX'YZ • Will use a T flip-flop triggered by PYZ

  36. How M inputs affect Z

  37. Solution • Z = M'Z + MZ' • Will use a T flip-flop triggered by M

  38. How M inputs affect Y

  39. Solution • Y = M'Y + MYZ + M Y'Z' • Will use a T flip-flop triggered by MZ'

  40. How M inputs affect X

  41. Solution • X = M'X + MXY + MXZ +MX'Y'Z' • Will use a T flip-flop triggered by MY'Z'

  42. How P inputs affect O

  43. Solution • O = PXYZ

  44. How M inputs affect U

  45. Solution • U = MX'Y'Z' • Will use a T flip-flop triggered by MY'Z'

  46. Summary • Flip-flops • Z: T flip-flop triggered by P + M • Y: T flip-flop triggered by PZ + MZ' • X: T flip-flop triggered by PYZ + MY'Z' • Outputs • O = PXYZ • U = MX'Y'Z'

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