Transactional memory
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Transactional Memory. Student Presentation: Stuart Montgomery. Why?. Shan Lu, et. al, Learning From Mistakes. Avoid explicit locking Non-blocking: can’t deadlock Higher level abstraction for the programmer

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Transactional Memory

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Transactional memory

Transactional Memory

Student Presentation:

Stuart Montgomery

CS5204 – Operating Systems

Transactional memory


Shan Lu, et. al, Learning From Mistakes

  • Avoid explicit locking

  • Non-blocking: can’t deadlock

  • Higher level abstraction for the programmer

    • “The value of STM is that it allows you to focus on designing applications which happen to scale instead of the mechanisms employed to scale those applications.”

CS5204 – Operating Systems

What is tm

What is TM?

  • Regions of code that manipulate values (memory) atomically

  • ACID: Atomicity, Consistency, Isolation, Durability

  • All or nothing

  • Atomic Regions - 1977 (Lomet)

  • Hardware TM - 1986/1993 (Knight/Herlihy and Moss)

  • Software TM -1995 (Shavit and Touitou)

CS5204 – Operating Systems

Hardware transactional memory

Hardware Transactional Memory

CS5204 – Operating Systems

Hardware tm

Hardware TM

  • Transactions operate on hardware data cache

  • Changes to memory are committed atomically to other caches

  • A natural extension of Load-Linked/Store-Conditional

    • LL/SC provides an atomic update to a single word of memory

    • HTM extends LL/SC to create groups of atomic instructions

  • Generally, HTM systems are bounded

    • Restricts the size of a transaction!

CS5204 – Operating Systems

Hardware tm concepts

. . .







Shared Memory

Hardware TM Concepts



  • Snoopy Cache Coherence – Goodman 1983

  • Caches listen to the bus to detect changes to their

    copy of the same cached address

CS5204 – Operating Systems

Hardware tm instructions

Hardware TM Instructions

  • LT

    • Read with NON-exclusive access (normal)

  • LTX

    • Read with exclusive access

    • Useful for when we anticipated writing to the read value soon

  • ST

    • Write to memory

  • Transaction State Instructions: Validate, Commit, Abort

  • XCOMMIT = Old vs. XABORT = New

  • Processor flags TSTATUS and TACTIVE

CS5204 – Operating Systems

Quick example

Quick Example

Herlihy and Moss, Transactional Memory: Architectural Support for Lock-Free Data Structures

shared int counter;

void process(int work){

int success = 0, backoff = BACKOFF_MIN;

unsigned wait;

while (success < work) {

ST(&counter, LTX(&counter) + 1);

if (COMMIT()) {


backoff = BACKOFF_MIN;


else {

wait = random() % (1 << backoff);

while (wait--);

if (backoff < BACKOFF_MAX)





CS5204 – Operating Systems

Hardware tm concerns

Hardware TM Concerns

  • Requires new hardware

  • Possibility of starvation with BUSY signals

    • Augment with queuing mechanism

  • Separate Transactional Cache or not

    • 1 cache: set size limits transaction size

      • But could use cache emulation in software

    • Extra abort, etc. logic applies to entire larger cache

    • Tradeoff between strong atomicity and efficiency

  • Hybrid Systems:

    • VTM

    • HASTM

    • Hybrid TM

CS5204 – Operating Systems

Notable htm implementations

Notable HTM Implementations

HTM Test on Rock Surpasses STM


  • Simulations

  • Sun’s Rock SPARC multicore processor

CS5204 – Operating Systems



  • Simulation results show that transactional memory matches or outperforms the best known locking techniques for simple benchmarks, even in the absence of priority inversion, convoying, and deadlock.

    • Fewer access to memory

  • Long transactions more likely to abort

  • Large transactions more likely to exceed TM cache size

CS5204 – Operating Systems

Software transactional memory

Software Transactional Memory

CS5204 – Operating Systems

Word based stm

Word-Based STM

CS5204 – Operating Systems

  • Shavit & Touitou

    • Historical

    • Each word of memory has an ownership record with old values

    • Transactions can “help” each other

  • Harris & Fraser

    • Track the deltas in transaction descriptors

    • Atomically commit transactions to the ownership records

Object based stm

Object-Based STM

Larus and Kozyrakis, Transactional Memory

CS5204 – Operating Systems

  • Dynamic STM (Herlihy et. al.)

  • Higher-level TM Objects

  • FSTM (Fraser)

    • Similar to Dynamic STM

  • Software tm design

    Software TM Design

    • Closed nesting

      • The child commits into the parent

    • Open nesting

      • The child commits to the world

    • Other considerations:

      • Direct/Deferred Update

      • Early/Late Conflict Detection

      • Conflict Resolution

        • E.g. Abort or Backoff

      • Nesting

      • Exceptions

        • Often ignored in STM designs

    figure adopted from [tcc-mcdonald-isca06]

    CS5204 – Operating Systems

    Case study stm net

    Case Study: STM.NET

    “But with the wisdom of age and hindsight, I do believe limited forms of TM could be wildly successful at particular tasks and yet would have avoided many of the biggest challenges with unbounded TM.”

    • Microsoft’s experiment 2008-2010, then dropped

    • Hook the C# JIT compiler, also investigated C++

    • Separate Haskell development

    • Joe Duffy’s retrospective on unbounded STM:

      • Applying transactions to intrinsically non-transactional operations (I/O)

        • Reading a block or file from the FS, output to the console, entry in the Event Log, web service calls, etc.

      • Weak vs. Strong Atomicity

        • Weak: Non-TM regions seeing the results of TM regions

      • Privatization

      • “Where is the killer App?”… most applications naturally parallel?

    CS5204 – Operating Systems

    Other notable stm implementations

    Other Notable STM Implementations

    Intel STM Compiler Prototype (C/C++)

    Sun DSTM2 (Java factories)

    Several libraries from Harris & Fraser

    Other languages: Haskell, LISP, Clojure, C#, OCaml, Perl

    CS5204 – Operating Systems



    • Hardware TM

      • Make memory access atomic by holding in a transactional cache

      • Caches for each CPU cooperate in determining use of memory locations

      • Faster

    • Software TM

      • Allows for a larger transactions and more design flexibility than HTM

      • Both word and object level granularity

      • Many possible design choices:

        • Strong/Weak Atomicity

        • Granularity

        • Conflict detection

        • Nested (Open or Closed)

    • Real-world implementations continue

      • Issues with particular design choices of STM.NET

    CS5204 – Operating Systems



    CS5204 – Operating Systems



    CS5204 – Operating Systems

    Weak atomicity problem

    Weak Atomicity Problem

    bool itIsOwned = false;

    MyObj x = new MyObj();

    atomic { // Tx0                          atomic { // Tx1

        // Claim the state for my use:           if (!itIsOwned)

        itIsOwned = true;                             x.field += 42;

    }                                        }

    int z = x.field;


    CS5204 – Operating Systems

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