ClubNet - November 2003 EE Department, Technion, Israel. Network on Chip (NoC). Evgeny Bolotin Supervisors: Israel Cidon, Ran Ginosar and Avinoam Kolodny. Outline. Motivation – SoC Communication Current Solutions NoC Concept QNoC Arch. & Design Process QNoC Example NoC Cost
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ClubNet - November 2003
EE Department, Technion, Israel
Network on Chip (NoC)
Israel Cidon, Ran Ginosar and Avinoam Kolodny
Motivation – SoC Communication
QNoC Arch. & Design Process
Asic - 0.35 mm
SoC - 0.1 mm
Taken From ITRS, 2001
Taken from W.J. Dally presentation: Computer architecture is all about interconnect (it is now and it will be more so in 2010) HPCA Panel February 4, 2002
From Board level into Chip level…
Original bus features:
Is it still?
What is Different?
Example1: Replace modules
Example2: Adapt Links
Example3: Trim Unnecessary (ports, buffers, routers, links)
Define Service Levels (SLs):
Flit (routing info)
Take full network and customize
using a-priori known parameters
Example: (Uniform mesh)
QNoC Cost : Total wire-length and FF-count
Representative Design Example, each module contains 4 traffic sources:
Calculated Link Load Relations:
Various Link BW allocations:
Fixed Network Configuration -Uniform Traffic
Network behavior under different traffic loads?
Uniform scenario (Same QoS):
Compare the cost of: