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ClubNet - November 2003 EE Department, Technion, Israel. Network on Chip (NoC). Evgeny Bolotin Supervisors: Israel Cidon, Ran Ginosar and Avinoam Kolodny. Outline. Motivation – SoC Communication Current Solutions NoC Concept QNoC Arch. & Design Process QNoC Example NoC Cost

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Network on Chip (NoC)

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Network on chip noc l.jpg

ClubNet - November 2003

EE Department, Technion, Israel

Network on Chip (NoC)

Evgeny Bolotin

Supervisors:

Israel Cidon, Ran Ginosar and Avinoam Kolodny


Outline l.jpg

Outline

Motivation – SoC Communication

Current Solutions

NoC Concept

QNoC Arch. & Design Process

QNoC Example

NoC Cost

Summary


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Growing Chip Density

  • Design complexity - high IP reuse

  • Efficient high performance interconnect

  • Scalability of communication architecture

1998

Asic - 0.35 mm

2003

SoC - 0.1 mm

Memory, I/O

P


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The Growing Gap: Computation vs. Communication

Taken From ITRS, 2001


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The Gap: Something to think about

Taken from W.J. Dally presentation: Computer architecture is all about interconnect (it is now and it will be more so in 2010) HPCA Panel February 4, 2002


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SoC Interconnect

  • Interconnect Dominates Delay and Power in VDSM

  • Doesn’t Scale with Technology:

    • interconnect power + delay more dominant as the technology improves

  • Globally Asynchronous Locally Synchronous (GALS ) Systems

    • distributed systems on single silicon substrate


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P

P

“Bus Inheritance”

From Board level into Chip level…


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B

Segmented Bus

B

Typical Solution-Bus

Shared Bus


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B

B

B

B

Typical Solution-Bus

Original bus features:

  • One transaction at a time

  • Central Arbiter

  • Limited bandwidth

  • Synchronous

  • Low cost

Multi-Level

Segmented

Bus

Segmented Bus

  • New features:

  • Versatile bus architectures

  • Pipelining capability

  • Burst transfer

  • Split transactions

  • Transaction preemption and resume

  • Transaction reordering…

Is it still?


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Well-known Industry Solutions

  • AMBA (Advanced Microcontroller Bus Architecture)Ownership: ARM

  • SiliconBackplane mNetworkOwnership: Sonics

  • Core-ConnectOwnership: IBM


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Traditional SoC Nightmare

  • Variety of dedicated interfaces

  • Poor separation between computation and communication.

  • Design Complexity

  • Unpredictable performance


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Solution – Network on Chip

  • Networks are preferred over buses:

  • Higher bandwidth

  • Concurrency, effective spatial reuse of resources

  • Higher levels of abstraction

  • Modularity - Design Productivity Improvement

  • Scalability


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Solution – Network on Chip

  • Requirements:

  • Different QoS must be supported

    • Bandwidth

    • Latency

  • Distributed deadlock free routing

  • Distributed congestion/flow control

  • Low VLSI Cost


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NoC vs. “Off-Chip” Networks

What is Different?

  • Routers on Planar Grid Topology

  • Short PTP Links between routers

  • Unique VLSI Cost Sensitivity:

    • Area-Routers and Links

    • Power


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Example1: Replace modules

Replace

NoC vs. “Off-Chip Networks”

  • No legacy protocols to be compliant with …

  • No software  simple and hardware efficient protocols

  • Different operating env. (no dynamic changes and failures)

  • Custom Network Design – You design what you need!


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Adapt Links

NoC vs. “Off-Chip Networks”

Example2: Adapt Links

Example3: Trim Unnecessary (ports, buffers, routers, links)


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QNoC: QoS NoC

Define Service Levels (SLs):

  • Signaling

  • Real-Time

  • Read/Write (RD/WR)

  • Block-Transfer

  • Different QoS for each SL


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QNoC Architecture

  • Mesh Topology

  • Fixed shortest path routing (X-Y)

    • Simple Router (no tables, simple logic)

    • Power efficient communication

    • No deadlock scenario


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Flit

Flit

Flit (routing info)

Flit

Flit

Flit

Wormhole Packet:

QNoC Architecture

  • Wormhole Routing

    • For reduced buffering


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QNoC Wormhole Router


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QNoC Design Process

Take full network and customize

using a-priori known parameters


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QNoC Design Process - Optimization

  • Trim Unnecessary Resources

  • Adjust each link capacity according to its load

    • Equal link utilization across the chip

Example: (Uniform mesh)


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QNoC Design Process - Cost est.

QNoC Cost : Total wire-length and FF-count

  • Wire cost ~wire-length

  • Dynamic Power ~wire-lengthand U

  • Logic Cost ~ FF-count


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Design Example


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Design Example

Representative Design Example, each module contains 4 traffic sources:


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Uniform Scenario - Observations

Calculated Link Load Relations:


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Uniform Scenario - Observations

Various Link BW allocations:

Desired QoS


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ETEDelay

Real-Time

Traffic Load

Uniform Scenario - Observations

Fixed Network Configuration -Uniform Traffic

Network behavior under different traffic loads?

BLOCK

RD/WR

Signaling


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QNoC vs. Alternative Solutions(4x4 mesh, uniform traffic)

Uniform scenario (Same QoS):

Cost

BUS

QNoC

PTP


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NoC Cost Scalability vs. Alternatives

Compare the cost of:

  • NoC

  • Non-Segmented Bus (NS-Bus)

  • Segmented Bus (S-Bus)

  • Point-To-Point (PTP)


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NoC Cost Scalability vs. Alternatives


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Summary

  • Why NoC?

  • What is Different in NoC

  • QNoC

  • NoC is Best


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