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ClubNet - November 2003 EE Department, Technion, Israel. Network on Chip (NoC). Evgeny Bolotin Supervisors: Israel Cidon, Ran Ginosar and Avinoam Kolodny. Outline. Motivation – SoC Communication Current Solutions NoC Concept QNoC Arch. & Design Process QNoC Example NoC Cost

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network on chip noc

ClubNet - November 2003

EE Department, Technion, Israel

Network on Chip (NoC)

Evgeny Bolotin

Supervisors:

Israel Cidon, Ran Ginosar and Avinoam Kolodny

outline
Outline

Motivation – SoC Communication

Current Solutions

NoC Concept

QNoC Arch. & Design Process

QNoC Example

NoC Cost

Summary

growing chip density
Growing Chip Density
  • Design complexity - high IP reuse
  • Efficient high performance interconnect
  • Scalability of communication architecture

1998

Asic - 0.35 mm

2003

SoC - 0.1 mm

Memory, I/O

P

the gap something to think about
The Gap: Something to think about

Taken from W.J. Dally presentation: Computer architecture is all about interconnect (it is now and it will be more so in 2010) HPCA Panel February 4, 2002

soc interconnect
SoC Interconnect
  • Interconnect Dominates Delay and Power in VDSM
  • Doesn’t Scale with Technology:
    • interconnect power + delay more dominant as the technology improves
  • Globally Asynchronous Locally Synchronous (GALS ) Systems
    • distributed systems on single silicon substrate
bus inheritance

P

P

“Bus Inheritance”

From Board level into Chip level…

typical solution bus

B

Segmented Bus

B

Typical Solution-Bus

Shared Bus

typical solution bus9

B

B

B

B

Typical Solution-Bus

Original bus features:

  • One transaction at a time
  • Central Arbiter
  • Limited bandwidth
  • Synchronous
  • Low cost

Multi-Level

Segmented

Bus

Segmented Bus

  • New features:
  • Versatile bus architectures
  • Pipelining capability
  • Burst transfer
  • Split transactions
  • Transaction preemption and resume
  • Transaction reordering…

Is it still?

well known industry solutions
Well-known Industry Solutions
  • AMBA (Advanced Microcontroller Bus Architecture)Ownership: ARM
  • SiliconBackplane mNetworkOwnership: Sonics
  • Core-ConnectOwnership: IBM
traditional soc nightmare
Traditional SoC Nightmare
  • Variety of dedicated interfaces
  • Poor separation between computation and communication.
  • Design Complexity
  • Unpredictable performance
solution network on chip
Solution – Network on Chip
  • Networks are preferred over buses:
  • Higher bandwidth
  • Concurrency, effective spatial reuse of resources
  • Higher levels of abstraction
  • Modularity - Design Productivity Improvement
  • Scalability
solution network on chip13
Solution – Network on Chip
  • Requirements:
  • Different QoS must be supported
    • Bandwidth
    • Latency
  • Distributed deadlock free routing
  • Distributed congestion/flow control
  • Low VLSI Cost
noc vs off chip networks
NoC vs. “Off-Chip” Networks

What is Different?

  • Routers on Planar Grid Topology
  • Short PTP Links between routers
  • Unique VLSI Cost Sensitivity:
      • Area-Routers and Links
      • Power
noc vs off chip networks15

Example1: Replace modules

Replace

NoC vs. “Off-Chip Networks”
  • No legacy protocols to be compliant with …
  • No software  simple and hardware efficient protocols
  • Different operating env. (no dynamic changes and failures)
  • Custom Network Design – You design what you need!
noc vs off chip networks16

Adapt Links

NoC vs. “Off-Chip Networks”

Example2: Adapt Links

Example3: Trim Unnecessary (ports, buffers, routers, links)

qnoc qos noc
QNoC: QoS NoC

Define Service Levels (SLs):

  • Signaling
  • Real-Time
  • Read/Write (RD/WR)
  • Block-Transfer
  • Different QoS for each SL
qnoc architecture
QNoC Architecture
  • Mesh Topology
  • Fixed shortest path routing (X-Y)
    • Simple Router (no tables, simple logic)
    • Power efficient communication
    • No deadlock scenario
qnoc architecture19

Flit

Flit

Flit (routing info)

Flit

Flit

Flit

Wormhole Packet:

QNoC Architecture
  • Wormhole Routing
    • For reduced buffering
qnoc design process
QNoC Design Process

Take full network and customize

using a-priori known parameters

qnoc design process optimization
QNoC Design Process - Optimization
  • Trim Unnecessary Resources
  • Adjust each link capacity according to its load
    • Equal link utilization across the chip

Example: (Uniform mesh)

qnoc design process cost est
QNoC Design Process - Cost est.

QNoC Cost : Total wire-length and FF-count

  • Wire cost ~wire-length
  • Dynamic Power ~wire-lengthand U
  • Logic Cost ~ FF-count
design example25
Design Example

Representative Design Example, each module contains 4 traffic sources:

uniform scenario observations
Uniform Scenario - Observations

Calculated Link Load Relations:

uniform scenario observations27
Uniform Scenario - Observations

Various Link BW allocations:

Desired QoS

uniform scenario observations28

ETEDelay

Real-Time

Traffic Load

Uniform Scenario - Observations

Fixed Network Configuration -Uniform Traffic

Network behavior under different traffic loads?

BLOCK

RD/WR

Signaling

qnoc vs alternative solutions 4x4 mesh uniform traffic
QNoC vs. Alternative Solutions(4x4 mesh, uniform traffic)

Uniform scenario (Same QoS):

Cost

BUS

QNoC

PTP

noc cost scalability vs alternatives
NoC Cost Scalability vs. Alternatives

Compare the cost of:

  • NoC
  • Non-Segmented Bus (NS-Bus)
  • Segmented Bus (S-Bus)
  • Point-To-Point (PTP)
summary
Summary
  • Why NoC?
  • What is Different in NoC
  • QNoC
  • NoC is Best
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