Register Transfers

Register Transfers PowerPoint PPT Presentation


  • 122 Views
  • Uploaded on
  • Presentation posted in: General

19 May 2012. 55:032 - Introduction to Digital Design. Page 2. Large System architecture. Large digital systems typically partitioned into:DatapathMany registers, lots of Combinational LogicMoves / processes system dataOperation specified by control word (from CU)Control UnitMany states and inp

Download Presentation

Register Transfers

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


1. Register Transfers 55:032 - Introduction to Digital Design

2. 19 May 2012 55:032 - Introduction to Digital Design Page 2 Large System architecture Large digital systems typically partitioned into: Datapath Many registers, lots of Combinational Logic Moves / processes system data Operation specified by control word (from CU) Control Unit Many states and inputs Specifies what DP does next Decisions made based on DP status information

3. 19 May 2012 55:032 - Introduction to Digital Design Page 3 Large System Block Diagram

4. 19 May 2012 55:032 - Introduction to Digital Design Page 4 Register Transfer The movement of data stored in registers and the processing performed on the data are referred to as Register Transfer Operations Register Transfer Language (RTL) captures register transfers and it’s components of: The registers within the system The operations performed on system data The control that defines the sequence of operation

5. 19 May 2012 55:032 - Introduction to Digital Design Page 5 Microoperations Each register has a set of elementary operations it can do E.G. Load, Increment, Shift, etc. The combination of elementary register ops and combinational functions define simple system operations These are the Microoperations of the system Usually performed in a single clock cycle Sequence of ?-ops specified by control unit

6. 19 May 2012 55:032 - Introduction to Digital Design Page 6 Register Transfer Notation General form of register transfer expression: Destination Register ? Information source where ‘?‘ is the replacement operator Destination register contents is replaced by source information Ususally done at the next clock Transfers may be conditional Condition: Dest. ? Source

7. 19 May 2012 55:032 - Introduction to Digital Design Page 7 Register Transfer Notation Registers denoted by uppercase letters E.G. A, PC, R0, SP Individual FFs indexed as either big-endian or little-endian (need to define which) BIG: MSB is 1, LSB is n LITTLE: LSB is 0, MSB is n-1 Register parts referred to by H, L or bit range PC(H), PC(L), IR(15:8), IR(7:0)

8. 19 May 2012 55:032 - Introduction to Digital Design Page 8 Register Transfer Notation Register transfer source information may be A single source register External input data Results of combinational logic operation E.G. R0 ? R1 IR ? M[AR] (memory read at loc AR) PC ? PC + 1

9. 19 May 2012 55:032 - Introduction to Digital Design Page 9 Register Transfer Operations The microoperations is a system generally classified into four types Transfer - moving data from register to register Arithmetic - signed and unsigned arithmetic Logical - bitwise and, or, not, etc. Shift - shifts, rotates, etc. See table 7-2 in text for correspondence between RTL and VHDL

10. 19 May 2012 55:032 - Introduction to Digital Design Page 10 Arithmetic Microoperations Basic addition and subtraction Signed and unsigned Negative number representation to be used must be stated Increment and decrement Comparison (output is true or false!) Multiplication might be included Very complex combinational logic Division is rarely included

11. 19 May 2012 55:032 - Introduction to Digital Design Page 11 Logical Microoperations Include the bitwise AND, OR, NOT logical operations You may see new symbols used in RTL AND - ? OR - ? These are needed to reduce confusion between arithmetic and logical operations Logical ops used for bit set, clear masking

12. 19 May 2012 55:032 - Introduction to Digital Design Page 12 Shift Microoperations Don’t have standard operator symbols You should include a key for anything outside of the author’s definition Include left and right shifts and rotates Logical and arithmetic shifts Must properly handle sign bit, overflow cond. Shift microoperations do not necessarily imply a shift register R1 ? sr R2 (no SR needed here)

13. 19 May 2012 55:032 - Introduction to Digital Design Page 13 Transfer Operations Each is simple; complexity results from designing hardware to perform all defined transfers for each register Many data sources (need to select) Different control for each source Selection of the data source may be via: Multiplexers Data bus

14. 19 May 2012 55:032 - Introduction to Digital Design Page 14 Multiplexer-based Transfer You have a limited number of local data sources E.G. K1: R1 ? R3 K2: R1 ? R1 + R2 Two sources are defined; use a 2 to 1 mux Small combinational function need to translate the K1 and K2 controls to the mux select and register load control signals

15. 19 May 2012 55:032 - Introduction to Digital Design Page 15 Multiplexer-based Register Transfer

16. 19 May 2012 55:032 - Introduction to Digital Design Page 16 Multiple Register Transfers with MUXes Systems usually have multiple destination registers, each with multiple sources Common to have multiple reg. transfers at the same time Designer has some choice of implementation Use separate multiplexer for each destination Use a shared multiplexer for all dest. Registers Perform the source selection function with three-state outputs

17. 19 May 2012 55:032 - Introduction to Digital Design Page 17 Dedicated Multiplexers

18. 19 May 2012 55:032 - Introduction to Digital Design Page 18 Shared Multiplexer

19. 19 May 2012 55:032 - Introduction to Digital Design Page 19 Selection via Three State Outputs

  • Login