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T2.2 Task (1/2). Task T2.2: PV-aware device simulation

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T2.2 Task (1/2)

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T2 2 task 1 2

T2.2 Task (1/2)

  • Task T2.2: PV-aware device simulation

  • Focus in this task is on activities to include variability in device simulation tools. TCAD will be used to assess various device architectures in standard CMOS but also in other technologies concerning variability, to identify major sources for variability on simulation level already; process sensitivities will be investigated. New methods will be developed to generate statistical circuit simulation parameter through TCAD, with smart approaches (other than brute force). Furthermore mixed mode device/circuit simulations will be carried out.

  • Partners: UNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS

  • UNGL will identify the sources of statistical variability in 45 nm CMOS and predict the statistical variability in 32 and 22 nm technology generation devices and advanced NVM devices based on statistical 3D drift diffusion simulations. The simulations will be carried out with the UNGL 3D ‘atomistic’ statistical simulator GARAND. This semi-commercial tool includes random discrete dopants, line edge roughness, poly silicon and high-k granularity, and interface and body thickness variations. Methodology will be developed to capture the transport variability associated with the above variability sources using 3D Monte Carlo simulations and the results will be folded in the Drift-Diffusion simulations using appropriate mobility models. The simulator will be interfaced to the TCAD process simulation tools developed in task 2.1 and validated in respect of 45 nm technology devices from partners in the consortium. This will allow the identification of the major sources of statistical variability at this technology generation. The simulator will be than used to predict the magnitude of statistical variability in 32 nm Ultra Thin Body SOI transistors developed by LETI and 22 nm technology devices with novel architecture. ST-I will translate behavioral models which take into account the statistical information of process fabrication steps into device electrical performance. Parameter sensitivities will be studied for a wide range of electrical performance. The objective of the POLI contribution is to investigate efficient methods to develop physics-based statistical models and PV aware modeling with the use of smart TCAD approaches, based on sensitivity evaluation techniques, and to link such approaches to suitable compact model structures. The main object will be mainstream planar bulk down to CMOS 45/32nm. Starting from DC sensitivities and statistical analysis, linking random process parameters to random "static" device performances (such as the threshold voltage), extensions to the dynamic case, based on time- and/or spectral-domain approaches, will be considered. STF2 will extrapolate the results generated during the first 24 months of MODERN to more advanced nodes. Various advanced device architectures such as planar Ultra-Thin-Body and BOX (UTB²), FinFET, or Planar Double Gate All-Around will be compared in terms of robustness to variability (both process-induced and local). For this comparison 16nm design rules will be estimated and used furtheron to estimate the minimum SRAM bit-cell size for each structure guaranteeing a proper functionality of a 64Mbit array.

Project Review Meeting

Crolles, June 22, 2009


T2 2 task 2 2

T2.2 Task (2/2)

  • Task T2.2: PV-aware device simulation (cont’)

  • The device simulation will be carried out using the analytical software MASTAR, which has been used to calculate ITRS roadmaps 2005 and 2007. IMEP will focus on the modeling of variability in advanced CMOS devices (bulk and thin film SOI), and on atomistic simulations of variability in thin film CMOS devices. The work will be carried out in cooperation with STF2. Specific modelling of the influence of new variability sources like metal gate work function fluctuations, thin film thickness variation, RTS noise will be investigated using TCAD and simple analytical models. The latter will also be introduced into MASTAR platform, in collaboration with STF2, for new technology specification prediction. UNET will put emphasis on the device simulation of memory cells, transistors for high-performance logic circuits and for low-power mixed-mode applications: At the beginning a methodology will be defined to evaluate the impact of process tolerances and intrinsic variability on the dispersion of electrical parameters with computationally efficient TCAD. Viable modelling approaches to efficiently incorporate new physics phenomena and their fluctuations in future devices will be worked out, taking into account the impact of variations of the dielectric thickness, channel doping and stress conditions. In addition a methodology will be defined to evaluate the impact of PV on a single cell within a memory array. Mixed-mode device/circuit simulation methodologies will be looked into to analyze the impact of fluctuations on the performance of simple digital and analog circuit blocks. The objective of the work of NMX is to study the impact random dopant, edge roughness, and trap position on scaled NVM cells of Non Volatile Memory technologies from 32nm technology node and below. It’s about to push the implementation of the capability to treat individual dopant atoms and individual traps instead of dopant concentrations used nowadays in commercial device simulators. SNPS will enhance the methods of modeling process induced geometrical variations of the devices. The goal is to find methods that allow the direct calculation of uncorrelated geometrical variations on device electrical characteristics. SNPS will evaluate and improve its existing TCAD models with respect to the treatment of individual dopants and traps in silicon in device modelling tools.

Project Review Meeting

Crolles, June 22, 2009


Device simulation t2 2 deliverables

Device Simulation: T2.2 Deliverables

Task Leader: [email protected]

Project Review Meeting

Crolles, June 22, 2009


T2 2 review

T2.2 Review

For each deliverable

  • Identify contributing partners

  • Identify deliverable leaders

  • Taking charge of Deliverables

Project Review Meeting

Crolles, June 22, 2009


T2 2 review activity done so far

T2.2 Review: Activity done so far

  • Discussion and partial agreement on template devices

    Bulk MOSFETs

    45nm STF2 - availability: possibly recalibration

    32nm STF2 - availability? 5wayNDA in progress

    22nm ???

    16nm ???

    FD SOI MOSFETs

    32nm LETI (T2.3) Is it confirmed by Leti?

    22nm LETI (T2.3)

    16nm LETI (T2.3)

Project Review Meeting

Crolles, June 22, 2009


T2 2 review activity done so far1

T2.2 Review: Activity done so far

  • Discussion and partial agreement on template devices

    FinFETS

    22nm ??? Note that NXP might provide HW within T2.3

    16nm ???

    None Volatile Memory (NVM)

    NMX, under NDA

    SiC

    ST-I, conditions to be defined

    GaN/AlGaN

    ST-I, conditions to be defined

Project Review Meeting

Crolles, June 22, 2009


T2 2 review activity done so far2

T2.2 Review: Activity done so far

  • Discussion and partial agreement on template devices

    Who wants/needs access to the different template devices.

    Prepare the necessary NDA.

    Now the deliverables covered but partial NDA will be developed/distributed

    Format of data to be exchanged

Project Review Meeting

Crolles, June 22, 2009


T2 2 review activity done so far3

T2.2 Review: Activity done so far

  • Format of data to be exchanged

Project Review Meeting

Crolles, June 22, 2009


T2 2 review activity done so far4

T2.2 Review: Activity done so far

  • Review of needs for statistical TCAD simulation

    • All major semiconductor players contacted

    • 25 responses so far from TCAD and device engineers including NEC, Fujitsu, Chartered, IBM, Freescale, NXP, Panasonic, Intel, Numonix, Toshiba, Infineon, Samsung, Renesas, Hitachi, Altera, Sony

    • TSMC declined to participate

    • Still awaiting response from ST-F

Project Review Meeting

Crolles, June 22, 2009


T2 2 review activity done so far by partners

T2.2 Review: Activity done so far by partners

  • NMX

    • Preliminary discussion (internal and with UNGL/SNPS) on NMX needs and possible solutions

    • Investigating PV effects related to doping and traps in NVM cells using a 3D Drift-Diffusion approach

  • POLI/G

    • Preliminary assessment of PV-aware commercial TCAD tools, tele-meeting with Synopsys

    • General agreement w/ SNPS on defining a common framework of operation (explore analog applications, assess sources of fluctuations etc.)

Project Review Meeting

Crolles, June 22, 2009


T2 2 review activity done so far by partners1

T2.2 Review: Activity done so far by partners

  • IMEP

    • Self-consistent calculations based on Full-3D real-space NEGF and Coupled mode-space (CMS) NEGF

      Recent results

      Surface-roughness scattering in SiNWs and DG MOSFETs

      Remote Coulomb scattering in SiNWs

      Electron-phonon scattering in SiNWs

    • Simple modelling of variability for MAstar (coll with ST)

    • Analytical model for pocket impact on MOSFET with data from T2.3 on 45nm CMOS

Project Review Meeting

Crolles, June 22, 2009


T2 2 review plan for d2 2 1

T2.2 Review: Plan for D2.2.1

  • Collect and analyze the survey of requirements

  • Invite TCAD tool vendor to declare the capabilities of their tools to asress the requirements

  • Prioritization related to the MODERN partners neeeds

Project Review Meeting

Crolles, June 22, 2009


T2 2 review plan for d2 2 2

T2.2 Review: Plan for D2.2.2

  • Finalize the relevant template devices

  • Identify the players

  • Complete the necessary NDAs

  • Identify the variability sources to be included in the simulations

  • Agree on specifications and parameters describing the variability sources

  • Agree on simulation sets and perform simulations

  • Collect and compare results

Project Review Meeting

Crolles, June 22, 2009


T2 2 review plan for d2 2 21

T2.2 Review: Plan for D2.2.2

  • In order to receive half of its MODERN funding from Scottish Enterprise UGLA had to create a company Gold Standard Simulations (GSS)

  • The company will provide simulations services of statistical variability using software developed by UGLA and Grid technology

  • UGLA will subcontract production simulations of 45nm, 32nm and 22nm devices to GSS

  • GSS will offer similar cervices to other companies on commercial basis

  • GSS will also offer services in statistical compact model extraction, statistical circuit simulation and statistical standard cell characterization usin in-house tools

Project Review Meeting

Crolles, June 22, 2009


T2 2 review plan for d2 2 3

T2.2 Review: Plan for D2.2.3

  • Finalize the relevant template devices

  • Identify the players

  • Complete the necessary NDAs

  • Identify the variability sources to be included in the simulations

  • Agree on specifications and parameters describing the variability sources

  • Agree on simulation sets and perform simulations

  • Collect and compare results

Project Review Meeting

Crolles, June 22, 2009


T2 2 review issues

T2.2 Review: Issues

  • Ensure that the simulated and the measured devices are identical

  • Italy and UK contracts not signed yet…

  • Agree on tool features definition (D2.2.1=>D1.1)

    • Integration in SNPS platform

    • Issues on 3D meshing strategy and mobility models

  • Confirm time line for tool availability

    • M12 for doping/traps (D2.2.2), M24 for geometry (D5.3.2)

  • Choose bestbenchmarks

Project Review Meeting

Crolles, June 22, 2009


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