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SLAAC SLD Update

DARPA. DARPA. SLAAC SLD Update. Steve Crago USC/ISI September 14, 1999. Second-Level Detection. Identification. Detection. PGA. Joint STARS Advance Workstation (JAWS) ATR Results Display. ESAR Image. Focus of Attention. Indexer (SLD). Belief Management (Fusion Executive). MPM.

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SLAAC SLD Update

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  1. DARPA DARPA SLAAC SLD Update Steve Crago USC/ISI September 14, 1999

  2. Second-Level Detection Identification Detection PGA Joint STARS Advance Workstation (JAWS) ATR Results Display ESAR Image Focus of Attention Indexer (SLD) Belief Management (Fusion Executive) MPM MSE CRM LPM Second-Level Detection SAR Image Annotated SAR Image Goal 200x performance improvement over old custom hardware T72 T72 *Not Joint STARS imagery

  3. Interface • Input • Chips (regions of interest, 8-bit pixels) • Bright and Surround Templates (expected SAR reflection and absorption, 1-bit pixels) • Output • Hypothetical target matches

  4. SLD Search Space Chip Template 32 pixels 64 pixels Search Space 15 pixels *Not Joint STARS imagery 48 pixels Chip

  5. Computation For each position in the search space: SM(i, j) = SSB(u,v)M(i+u, j+v), 8-bit additions P1 Shape Sum • Calculate average intensity of chip pixels at positions expected to reflect signal TH(i,j) = SM(i,j)/BC - Bias • Count number of pixels that exceed average intensity under “on” bright template pixels P2 Threshold BS(i, j) = SSB(u,v)[M(i+u, j+v)<TH(i,j)] 8-bit comparisons 1-bit additions SS(i, j) = SSS(u,v)[M(i+u, j+v)<TH(i,j)] 8-bit comparisons 1-bit additions • Counter number of pixels that are less than average intensity under “on” surround template pixels P3 Bright Sum P4 Surround Sum Q(i, j) = [BS(i, j) + SS(i, j)]*100 50 50 P5 Hit Quality Check hit conditions, calculate hit quality, and return 2 highest hit quality scores

  6. ACS Implementation • Compute independent search space pixels in parallel (15 - 200 computational elements per FPGA) Host Highest Quality Hits (Chip, Template IDs, location) Packed 8-bit pixels Chip Pixels Adaptive Computing Element Packed bits Template Memory

  7. I/O Requirements • Each eight-bit chip pixel used for 550 operations per match task • Each FIFO element contains 8 chip pixels • Each FIFO elements contains enough operands for 3600 operations  I/O will not be a bottleneck any time soon!

  8. Memory Requirements • Template pixels are only 1 bit (each memory access provides 18 operands) • Computation uses one template bit per cycle • Pixels are broadcast to all compute elements that are working on a single match task • Multiple ports for parallel match tasks reduce logic complexity  Memory bandwidth will not be a bottleneck any time soon, but ports are helpful!

  9. Virtex Features • Chip pixel alignment pipeline • BlockSelectRAM+ can replace logic cells • Could buy some speed • Template-specific reconfiguration • Potential speedup due to sparseness of templates • Clear win not yet clear

  10. Performance Projections

  11. Schedule • Single-chip implementation working • Full Wildforce implementation: 9/99 • SLAAC-2 implementation: 9/99? • Virtex implementation: ??? • Remap to use additional logic should be easy • Utilization of BlockSelectRAM+ will take a little more time, but straightforward

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