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BNL Update and Issues

BNL Update and Issues. HV Multiplexing update DC-DC stave width SP Stave PPB replacement Trigger document. D. Lynn, May, 25 2012. HV Multiplexing. Quad HV switching box using commercial SiC JFETs built and tested at BNL. Each channel biased BNL module with no change in ENC and DTN noise.

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BNL Update and Issues

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  1. BNL Update and Issues HV Multiplexing update DC-DC stave width SP Stave PPB replacement Trigger document D. Lynn, May, 25 2012

  2. HV Multiplexing • Quad HV switching box using commercial SiC JFETs built and tested at BNL. Each channel biased BNL module with no change in ENC and DTN noise. • Box rated to 500V • Shipped to RAL for stavelet testing

  3. HV Multiplexing • Mounted two boards with 4 dies, and one board with 2 die. • Plan was to test boards to 700 V and characterize die prior to irradiation • Started testing with practice 2-die board. Sparking occurred between 500-700 V • Encapsulated both 4-die boards. Both ran to 700 V with no problem. • SiC company uses encapsulation also. But I think improved wire bonding pattern should help Board mounted with four SiC JFETs Encapsulated Board

  4. Leakage Current • Die leakage current more varied than that of packaged parts. • Reason not yet known

  5. JFET performance • Transistor characteristics of all eight die very good • Will gamma irradiate these very soon

  6. HV Multiplexing Plan • Irradiate two boards soon with gammas • Ordered more die. We are building three more boards. Intention is to irradiate these with protons in August • Still need to investigate other devices

  7. Shieldless LBNL DC-DC Stavelet

  8. Full length DC-DC stave • Uses CF tubes, although could be built with Al/polycarbonate sides. What do we want? Has to be compatible with module mounting fixture at RAL. • What should be facing width? • What are bus cable widths? More information regarding the converter widths. Will assume stays as is (13.5mm width) until we hear otherwise.Regards, Ashley-------- Original Message -------- Subject: RE: RE: Future DC-DC Developments for ATLAS Strips Date: Fri, 27 Apr 2012 15:58:18 +0000 From: Georges Blanchot<Georges.Blanchot@cern.ch> To: Ashley Greenall<ashley@hep.ph.liv.ac.uk> Hello, We will try to keep the width the same as on the SM01C and STV10 power modules, I think it is 13.5 mm. A width of 5mm is too narrow. Georges

  9. Full length SP Stave • What is timescale? • Will this be chain of modules or chain of hybrids? • Do we want PPB (chain of hybrids), PPB2 (chain of modules), Ashley’s PPBR* board, or new board? Mitch’s SPP compatible with PPB and PPB2. New board needed to be compatible with SPP and star configuration.

  10. Trigger Document L0 accept rate: 500 kHz L0 latency: ~ 5-6 ms L1 accept rate: 200 kHz L1 latency: 20 ms • Following Stanford, subsystems were asked if the could achieve the trigger performance in box to the right • I along with others looked into the question. See M. Warren’s talk at the the May 8 ITK-Subcomitte meeting. • I did a less sophisticated calculation than Matt’s but got the same answer. My calculation is in the backup documents to Matt’s presentation. • For reference I put the updated version here. The reason I mention this is that some of you may be interested in how the trigger/occupancy/GBT rates/ HCC data rates are related; until a few weeks ago I had no understanding of this. • Two conclusions are however: with today’s technology it appears the barrel can just about achieve this rates if we discard error correction in the GBT. • The real test on the trigger rates will be the petals. And in particular the ROI (Region-of-interest) algorithm for the ABC130 appears to fail for the petals….work will be focusing on this in the future.

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