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Progettazione di circuiti e sistemi VLSI. Anno Accademico 2010-2011 Lezione 6 18.3.2011 La logica combinatoria. Combinational vs. Sequential Logic. Combinational. Sequential. Output =. (. ). f. In, Previous In. Output =. (. ). f. In.

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Progettazione di circuiti e sistemi VLSI

Lezione 6

18.3.2011

La logica combinatoria

La logica combinatoria

Combinational vs. Sequential Logic

Combinational

Sequential

Output =

(

)

f

In, Previous In

Output =

(

)

f

In

La logica combinatoria

At every point in time (except during the switching

transients) each gate output is connected to either

V

or

V

via a low-resistive path.

DD

ss

The outputs of the gates assume at all times the value

of the Boolean function, implemented by the circuit

(ignoring, once again, the transient effects during

switching periods).

This is in contrast to the

dynamic

circuit class, which

relies on temporary storage of signal values on the

capacitance of high impedance circuit nodes.

Static CMOS Circuit

La logica combinatoria

Static Complementary CMOS

VDD

In1

PMOS only

In2

PUN

InN

F(In1,In2,…InN)

In1

In2

PDN

NMOS only

InN

PUN and PDN are dual logic networks

La logica combinatoria

NMOS Transistors in Series/Parallel Connection

• Transistors can be thought as a switch controlled by its gate signal
• NMOS switch closes when switch control input is high

La logica combinatoria

Threshold Drops

VDD

VDD

PUN

S

D

VDD

D

S

0  VDD

0  VDD - VTn

VGS

CL

CL

CL

CL

PDN

VDD 0

VDD |VTp|

VGS

D

S

VDD

S

D

La logica combinatoria

Complementary CMOS Logic Style

La logica combinatoria

Example Gate: NAND

P

La logica combinatoria

B

A

C

D

Complex CMOS Gate

OUT = D + A • (B + C)

A

D

B

C

La logica combinatoria

Constructing a Complex Gate

La logica combinatoria

Cell Design

• Standard Cells
• General purpose logic
• Can be synthesized
• Same height, varying width
• Datapath Cells
• For regular, structured designs (arithmetic)
• Includes some wiring in the cell
• Fixed height and width

La logica combinatoria

Standard Cells

N Well

Cell height 12 metal tracks

Metal track is approx. 3 + 3

Pitch = repetitive distance between objects

Cell height is “12 pitch”

V

DD

Out

In

2

Rails ~10

GND

Cell boundary

La logica combinatoria

Standard Cells

2-input NAND gate

V

DD

A

B

Out

GND

La logica combinatoria

Stick Diagrams

Contains no dimensions

Represents relative positions of transistors

V

V

DD

DD

Inverter

NAND2

Out

Out

In

A

B

GND

GND

La logica combinatoria

Stick Diagrams

Logic Graph

A

X

PUN

j

C

B

C

X = C • (A + B)

i

VDD

X

C

i

B

A

j

A

B

A

PDN

B

GND

C

La logica combinatoria

Two Versions of C • (A + B)

A

C

B

A

B

C

VDD

VDD

X

X

GND

GND

La logica combinatoria

Consistent Euler Path

X

C

i

VDD

X

B

A

j

A

B

C

GND

La logica combinatoria

OAI22 Logic Graph

X

PUN

A

C

D

C

B

D

VDD

X

X = (A+B)•(C+D)

C

D

B

A

A

B

PDN

A

GND

B

C

D

La logica combinatoria

Example: x = ab+cd

La logica combinatoria

Properties of Complementary CMOS Gates Snapshot

High noise margins

:

V

and

V

are at

V

and

GND

, respectively.

OH

OL

DD

No static power consumption

:

There never exists a direct path between

V

and

DD

V

(

GND

.

SS

Comparable rise and fall times:

(under appropriate sizing conditions)

La logica combinatoria

CMOS Properties

• Full rail-to-rail swing; high noise margins
• Logic levels not dependent upon the relative device sizes;ratioless
• Always a path to Vdd or Gnd in steady state; low output impedance
• Extremely high input resistance; nearly zero steady-state input current
• No direct path steady state between power and ground; no static power dissipation
• Propagation delay function of load capacitance and resistance of transistors

La logica combinatoria

Switch Delay Model

Req

A

A

Rp

Rp

Rp

Rp

Rp

Rp

A

A

A

B

B

A

Cint

Rn

CL

CL

CL

Rn

Rn

Rn

Rn

B

B

A

A

A

Cint

NOR2

INV

NAND2

La logica combinatoria

Input Pattern Effects on Delay

• Delay is dependent on the pattern of inputs
• Low to high transition
• both inputs go low
• delay is 0.69 Rp/2 CL
• one input goes low
• delay is 0.69 Rp CL
• High to low transition
• both inputs go high
• delay is 0.69 2Rn CL

Rp

Rp

B

A

Rn

B

Cint

CL

Rn

A

La logica combinatoria

Delay Dependence on Input Patterns

A=B=10

A=1 0, B=1

A=1, B=10

Voltage [V]

time [ps]

NMOS = 0.5m/0.25 m

PMOS = 0.75m/0.25 m

CL = 100 fF

La logica combinatoria

Transistor Sizing

Rp

Rp

4

4

2

2

Rp

Rp

B

A

A

B

2

2

Rn

Cint

Cint

CL

CL

Rn

Rn

Rn

B

B

A

A

1

1

La logica combinatoria

Transistor Sizing a Complex CMOS Gate

B

8

6

4

3

A

C

8

6

4

6

D

OUT = D + A • (B + C)

A

2

D

1

B

2

C

2

La logica combinatoria

D

C

B

A

C3

C2

C1

CL

Fan-In Considerations

A

Distributed RC model

(Elmore delay)

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.

B

C

D

La logica combinatoria

tp as a Function of Fan-In

Gates with a fan-in greater than 4 should be avoided.

tp (psec)

tpHL

tp

tpLH

linear

fan-in

La logica combinatoria

tp as a Function of Fan-Out

All gates have the same drive current.

tpNOR2

tpNAND2

tpINV

tp (psec)

Slope is a function of “driving strength”

eff. fan-out

La logica combinatoria

tp as a Function of Fan-In and Fan-Out

• Fan-in: quadratic due to increasing resistance and capacitance
• Fan-out: each additional fan-out gate adds two gate capacitances to CL

tp = a1FI + a2FI2 + a3FO

La logica combinatoria

Fast Complex Gates:Design Technique 1

• Transistor sizing
• as long as fan-out capacitance dominates
• Progressive sizing

Distributed RC line

M1 > M2 > M3 > … > MN

(the mos closest to the

output is the smallest)

InN

MN

C3

C2

C1

CL

In3

M3

In2

M2

Can reduce delay by more than 20%; decreasing gains as technology shrinks

In1

M1

La logica combinatoria

Fast Complex Gates:Design Technique 2

• Transistor ordering

critical path

critical path

01

charged

charged

1

In1

In3

M3

M3

C2

C2

C1

C1

CL

CL

1

1

In2

In2

M2

discharged

M2

charged

1

In3

discharged

In1

charged

M1

M1

01

delay determined by time to discharge CL, C1 and C2

delay determined by time to discharge CL

La logica combinatoria

CL

CL

Fast Complex Gates:Design Technique 3

• Isolating fan-in from fan-out using buffer insertion

La logica combinatoria

Fast Complex Gates:Design Technique 4

• Reducing the voltage swing
• linear reduction in delay
• also reduces power consumption
• But the following gate is much slower!
• Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design)

tpHL= 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.69 (3/4 (CL Vswing)/ IDSATn )

La logica combinatoria

Sizing Logic Paths for Speed

• Frequently, input capacitance of a logic path is constrained
• Logic also has to drive some capacitance
• Example: ALU load in an Intel’s microprocessor is 0.5pF
• How do we size the ALU datapath to achieve maximum speed?
• We have already solved this for the inverter chain – can we generalize it for any type of logic?

La logica combinatoria

Buffer Example

In

Out

CL

1

2

N

(in units of tinv)

For given N: Ci+1/Ci = Ci/Ci-1

To find N: Ci+1/Ci ~ 4

How to generalize this to any logic path?

La logica combinatoria

Logical Effort

p – intrinsic delay (3kRunitCunitg) - gate parameter  f(W)

g – logical effort (kRunitCunit) – gate parameter  f(W)

f – effective fanout

Normalize everything to an inverter:

ginv =1, pinv = 1

Divide everything by tinv

(everything is measured in unit delays tinv)

Assume g = 1.

La logica combinatoria

Delay in a Logic Gate

Gate delay:

d = h + p

effort delay

intrinsic delay

Effort delay:

h = g f

logical effort

effective fanout = Cout/Cin

Logical effort is a function of topology, independent of sizing

Effective fanout (electrical effort) is a function of load/gate size

La logica combinatoria

Logical Effort

• Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates
• Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current
• Logical effort increases with the gate complexity

La logica combinatoria

Logical Effort

Logical effort is the ratio of input capacitance of a gate to the input

capacitance of an inverter with the same output current

g = 5/3

g = 4/3

g = 1

La logica combinatoria

Logical Effort of Gates

La logica combinatoria

Branching effort:

La logica combinatoria

Multistage Networks

Stage effort: hi = gifi

Path electrical effort: F = Cout/Cin

Path logical effort: G = g1g2…gN

Branching effort: B = b1b2…bN

Path effort: H = GFB

Path delay D = Sdi = Spi + Shi

La logica combinatoria

Optimum Effort per Stage

When each stage bears the same effort:

Stage efforts: g1f1 = g2f2 = … = gNfN

Effective fanout of each stage:

Minimum path delay

La logica combinatoria

Optimal Number of Stages

and given input capacitance of the first gate

Find optimal number of stages and optimal sizing

Substitute ‘best stage effort’

La logica combinatoria

Logical Effort

From Sutherland, Sproull

La logica combinatoria

Method of Logical Effort

• Compute the path effort: F = GBH
• Find the best number of stages N ~ log4F
• Compute the stage effort f = F1/N
• Sketch the path with this number of stages
• Work either from either end, find sizes: Cin = Cout*g/f

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

La logica combinatoria

Summary

Sutherland,

Sproull

Harris

La logica combinatoria

Power
• If well designed, the dynamic power prevails
• P=α01 CL VDD2

α01 is activity factor = 0.5 for the inverter

La logica combinatoria

Ratioed Logic

La logica combinatoria

Ratioed Logic

La logica combinatoria

La logica combinatoria

Pseudo-NMOS

La logica combinatoria

Pseudo-NMOS VTC

3.0

2.5

W/L

= 4

2.0

p

1.5

[V]

W/L

= 2

t

u

p

o

V

1.0

W/L

= 0.5

W/L

= 1

p

p

0.5

W/L

= 0.25

p

0.0

0.0

0.5

1.0

1.5

2.0

2.5

V

[V]

in

La logica combinatoria

Pass-Transistor Logic

La logica combinatoria

Pass-Transistor Logic

La logica combinatoria

Example: AND Gate

La logica combinatoria

NMOS-Only Logic

3.0

In

Out

2.0

[V]

x

e

g

a

t

l

o

V

1.0

0.0

0

0.5

1

1.5

2

Time [ns]

La logica combinatoria

NMOS Only Logic: Level Restoring Transistor

V

DD

V

DD

Level Restorer

M

r

B

M

2

X

M

A

Out

n

M

1

• Restorer adds capacitance, takes away pull down current at X

• Ratio problem

La logica combinatoria

Solution 2: Transmission Gate

C

C

A

A

B

B

C

C

C =

2.5 V

A =

2.5 V

B

C

L

C

= 0 V

La logica combinatoria

Resistance of Transmission Gate

La logica combinatoria

Transmission Gate XOR

B

B

M2

A

A

F

M1

M3/M4

B

B

La logica combinatoria

Delay in Transmission Gate Networks

2.5

2.5

2.5

2.5

V

V

V

V

V

V

1

i

n-1

i-1

i+1

n

In

C

C

C

C

C

0

0

0

0

(a)

R

R

R

R

eq

eq

eq

eq

V

V

V

V

V

1

n-1

i

i+1

n

In

C

C

C

C

C

m

(b)

R

R

R

eq

eq

eq

In

R

R

R

C

C

C

C

eq

eq

eq

C

C

C

C

(c)

La logica combinatoria

Delay Optimization

La logica combinatoria

Dynamic Logic

La logica combinatoria

Dynamic CMOS

• In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
• fan-in of n requires 2n (n N-type + n P-type) devices
• Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
• requires on n + 2 (n+1 N-type + 1 P-type) transistors

La logica combinatoria

Dynamic Gate

Clk

Mp

Clk

Out

Mp

Out

In1

In2

PDN

CL

A

In3

C

Clk

Me

B

Clk

Me

Two phase operation

Precharge (CLK = 0)

Evaluate (CLK = 1)

La logica combinatoria

Dynamic Gate

off

Clk

Mp

on

1

Clk

Out

Mp

((AB)+C)

Out

In1

In2

PDN

CL

A

In3

C

Clk

Me

B

off

on

Clk

Me

Two phase operation

Precharge (Clk = 0)

Evaluate (Clk = 1)

La logica combinatoria

Conditions on Output

• Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.
• Inputs to the gate can make at most one transition during evaluation.
• Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

La logica combinatoria

Properties of Dynamic Gates

• Logic function is implemented by the PDN only
• number of transistors is N + 2 (versus 2N for static complementary CMOS)
• Full swing outputs (VOL = GND and VOH = VDD)
• Non-ratioed - sizing of the devices does not affect the logic levels
• Faster switching speeds
• reduced load capacitance due to lower input capacitance (Cin)
• no Isc, so all the current provided by PDN goes into discharging CL

La logica combinatoria

Properties of Dynamic Gates

• Overall power dissipation usually higher than static CMOS
• no static current path ever exists between VDD and GND (including Psc)
• no glitching
• higher transition probabilities
• PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn
• low noise margin (NML)
• Needs a precharge/evaluate clock

La logica combinatoria

Solution to Charge Leakage

Keeper

Clk

Mp

Mkp

A

Out

CL

B

Clk

Me

Same approach as level restorer for pass-transistor logic

La logica combinatoria

Issues in Dynamic Design 2: Charge Sharing

Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness

Clk

Mp

Out

A

CL

CA

CB

B=0

Clk

Me

La logica combinatoria

Charge Sharing

V

DD

M

Clk

p

Out

C

L

M

A

a

X

C

a

M

=

B

0

b

C

b

M

Clk

e

La logica combinatoria

Solution to Charge Redistribution

Clk

Clk

Mp

Mkp

Out

A

B

Clk

Me

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

La logica combinatoria

CL1

CL2

Issues in Dynamic Design 3: Backgate Coupling

Clk

Mp

Out1

=1

Out2

=0

In

A=0

B=0

Clk

Me

Dynamic NAND

Static NAND

La logica combinatoria

Other Effects

• Capacitive coupling
• Substrate coupling
• Minority charge injection
• Supply noise (ground bounce)

La logica combinatoria

V

Clk

Clk

Mp

Mp

Clk

Out2

Out1

In

In

Clk

Clk

Me

Me

VTn

Out1

V

Out2

t

Only 0  1 transitions allowed at inputs!

La logica combinatoria

Domino Logic

Clk

Mp

Mkp

Clk

Mp

Out1

Out2

1  1

1  0

0  0

0  1

In1

In4

PDN

In2

PDN

In5

In3

Clk

Me

Clk

Me

La logica combinatoria

Why Domino?

Clk

Ini

Ini

Ini

Ini

PDN

PDN

PDN

PDN

Inj

Inj

Inj

Inj

Clk

Like falling dominos!

La logica combinatoria

Properties of Domino Logic

• Only non-inverting logic can be implemented
• Very high speed
• static inverter can be skewed, only L-H transition
• Input capacitance reduced – smaller logical effort

La logica combinatoria

Designing with Domino Logic

V

V

DD

DD

V

DD

Clk

M

Clk

M

p

p

M

r

Out1

Out2

In

1

PDN

In

PDN

In

2

4

In

3

Can be eliminated!

M

Clk

M

Clk

e

e

Inputs = 0

during precharge

La logica combinatoria

Footless Domino

The first gate in the chain needs a foot switchPrecharge is rippling – short-circuit current

A solution is to delay the clock for each stage

La logica combinatoria

Differential (Dual Rail) Domino

off

on

Clk

Clk

Mp

Mkp

Mkp

Mp

Out = AB

Out = AB

1 0

10

A

!A

!B

B

Clk

Me

Solves the problem of non-inverting logic

La logica combinatoria

np-CMOS

Clk

Me

Clk

Mp

Out1

1  1

1  0

In4

PUN

In1

In5

In2

PDN

0  0

0  1

In3

Out2

(to PDN)

Clk

Mp

Clk

Me

Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN

La logica combinatoria