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Part A Final

Part A Final. FPGA Setting Using Flash. Dor Obstbaum Kami Elbaz. Advisor: Moshe Porian . August 2012. Content. Introduction. Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo in Lab. Top Architecture. Micro Architecture. Testability. GUI.

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Part A Final

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  1. Part A Final FPGA Setting Using Flash Dor Obstbaum Kami Elbaz Advisor: Moshe Porian August 2012

  2. Content Introduction • Introduction • Top Architecture • Micro Architecture • Testability • GUI • Conclusions • Schedule • Demo in Lab Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  3. Motivation Software Hardware Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule - Pre determined - Static - Constantly updated - Dynamic How can we make the connection? Demo Non Volatile memory

  4. Motivation Introduction • Hardware operates by configuration written in the registers Top Architecture • Software writes up to date configuration in the FLASH memory Micro Architecture Testability GUI • FPGA setting using FLASH system does the connection Conclusions Schedule Demo FPGA setting using FLASH system registers FLASH memory Software Host Hardware System

  5. TOP Architecture Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  6. Project Goals Introduction • Creating Clients configured by registers that shall be updated using data stored in FLASH. • Implementing a data structure that will be used for data storage in FLASH and for data transmission to clients. • Setting an option for a host to read data from FLASH and write new data to it. • Implementing strong debugging capabilities including a useful GUI Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  7. Technical Demands Introduction • Hardware is VHDL Implemented and burned on Altera Cyclone II FPGA on DE2 development board • FLASH memory is spansion S29AL032D - 4MB also on DE2 development board • FPGA – Host communication via UART protocol • Internal communication via Wishbone protocol • Software GUI is MATLAB implemented Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  8. Message Pack Structure SOF Introduction • Start Of Frame 0x3C – 1 byte • Type – Which Client – 1 byte • Length of data bytes – 1 byte • Address in FLASH memory or register number – 3 bytes • Data – min burst 1 byte - max burst 256 bytes • Cyclic Redundancy Check (CRC) • End Of Frame 0xA5 Type Top Architecture Length Micro Architecture Testability Address GUI Conclusions Data Schedule Data Demo Length Data CRC EOF

  9. Write Transaction Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  10. Read Transaction Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  11. Micro Architecture Introduction Quick Reminder: • RX path • TX path • Wishbone units • Wait Client • Leds Client • Clock and Reset Detailed understanding: • Display Client Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  12. RX path Type Length SOF Introduction Type Address Top Architecture Length Address Micro Architecture CRC Testability EOF GUI SOF Type Conclusions Length Schedule Address Data Data Demo Data Data Data Data CRC EOF

  13. TX path Type Length Address Introduction Data Data Top Architecture Data Type SOF Micro Architecture Address EOF Testability Length GUI SOF Type Conclusions Length Type Schedule Address Address Demo Data Length Data Data Data Data Data CRC Data EOF Data Data CRC

  14. Wishbone communication Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  15. Wishbone master and slave Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  16. Wait Client Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  17. LEDS Client Introduction Top Architecture • Technical Demands: • Control 4 leds on DE2 board: • on/off • Blinking frequency • Operates on a 100 MHz clock • Inputs: Wishbone interface to configure registers • Outputs: 4 led_active signals • Generics: • - clk_freq_g • - timer_freq_g • - active_state_polarity_g Micro Architecture Testability GUI Conclusions Schedule Demo

  18. LEDS Client Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  19. Clock and Reset Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  20. Display client 1024 • Technical Demands: • VESA protocol • Operates on a 65 MHz clock • Produces 3 kinds of pictures: lines, columns, damka squares • control frame ROI and shape width and color • Supports any kind of Resolution and timing by Generics • Inputs: Wishbone interface to configure registers • Outputs: RGB, hsync, vsync, blank Introduction Top Architecture Micro Architecture Testability GUI 768 Conclusions Schedule Demo Our Configuration

  21. Display client Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo Integrated from RunLen project 100 MHz 65 MHz

  22. Display client Enable Lines Introduction Line ROI Top Architecture Line width Line color diff Micro Architecture RGB start val Testability GUI Enable Lines Line ROI Conclusions Line width RGB Schedule Demo Line color diff Integrated from RunLen project RGB start val

  23. Display client Introduction We Want Our Frames like These: Top Architecture Micro Architecture Testability GUI Conclusions And NOTlike these: Schedule Demo How do we keep Synchronization when registers Are updated?

  24. Synthetic Data Provider Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  25. Waveform Introduction Top Architecture Wishbone transactions configures registers Micro Architecture Testability GUI Conclusions Register Valid is ‘0’ while registers are updated Schedule Demo VESA generator requests data for a new frame Valid Data is supplied after 1 cycle

  26. Testability Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  27. Test Plan Introduction • Write Transactions • Read Transactions • Correct Functionality of Clients • System boundaries • System Generics Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  28. Test Environment Introduction Top Architecture DUT Micro Architecture Testability GUI Conclusions Schedule Demo

  29. Example: Generating the correct Frame • Generate a Text File with a write Transaction to Display Client • Run Simulation Introduction Wrong! Top Architecture • Analyze the results Micro Architecture • Fix Bugs if necessary Testability Correct • Run and Analyze again GUI Conclusions Schedule Demo DUT

  30. GUI Build the Transition Introduction Register Description Top Architecture Micro Architecture Packet Window Testability Text files control GUI Conclusions Change/Remove CRC, SOF, EOF Schedule Demo RX and TX debug window Messages for user window

  31. GUI and Simulations Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  32. Synthesis Results Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  33. Timing Results Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  34. Debugging the hardware Introduction Problem: First programming on FPGA…nothing happens Source: The reset button on the DE2 board is active low while our generic for reset is active high Solution: Change the reset_activity_polarity_g generic to ‘0’. Conclusion: The ‘Programming indication led’ is found useful. Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  35. Debugging the hardware Introduction Problem: Writes effect only register address 0. Source: A FF was not implemented by synthesis because ‘clk’ signal was not mentioned in a process sensitivity list Solution: Using signaltap found a bug at the address advancer (inside clients registers) Conclusion: When a problem occurs at the hardware but not on simulation, take a look at Quartus warnings and compilation report Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  36. Debugging the hardware Introduction Problem: No Display Source: Forgot to allocate one pin in the pin allocation script Solution: Using signaltap found hardware is OK. Pin allocation script was repaired Conclusion: Double check the pin allocation script Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  37. What have we learned so far? Introduction • Planning and Specifying a Project • Writing reusable generic code • Protocols: UART, Wishbone, VESA • Integration of many components • Verify logic correctness using waveforms, text files, BMP files and scripts • Testing our hardware using GUI and debug with signaltap • Documentation of the work done • Code Review and running a project diary are useful tools Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  38. Schedule Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

  39. Introduction Top Architecture Micro Architecture Testability GUI Conclusions Schedule Demo

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