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Controlled Transverse Blowup with ADT “plan” for MD block #3 / 2011 W. Hofle

Controlled Transverse Blowup with ADT “plan” for MD block #3 / 2011 W. Hofle With participation and input from: S. Redaelli , R. Schmidt, D. Valuch. Motivation and procedure for transverse blow-up with ADT (1) efficient procedure for transverse loss maps

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Controlled Transverse Blowup with ADT “plan” for MD block #3 / 2011 W. Hofle

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  1. Controlled Transverse Blowup with ADT “plan” for MD block #3 / 2011 W. Hofle With participation and input from: S. Redaelli, R. Schmidt, D. Valuch W. Hofle LSWG - 16. August 2011

  2. Motivation and procedure • for transverse blow-up with ADT (1) • efficient procedure for transverse loss maps • spec: loose equivalent of one nominal bunch on timescale of 1s  10s • needed at 450 GeV and 7 TeV • time-gating to target individual slices of beam (no need to re-fill for a 2nd map) • 1 fill with 10 probes for setting-up during the MD • 2 x fills with 12 nominal bunches (two schemes are proposed) for demonstration • evaluate feasibility to do loss maps with this technique on full beam • restrict MD to 450 GeV, maximum intensity 12 nominal bunches • gating to be checked with 10 probe bunches W. Hofle LSWG - 16. August 2011

  3. Motivation and procedure • for transverse blowup-up with ADT (2) • aperture measurements • use single probe beam with 1x1010 per bunch • restriction to 450 GeV only ? • slow and smooth blowup  white noise, full spectrum thought to be best • observe losses around ring  identify aperture limit • at regular intervals wirescans to monitor the emittances quantification • no gating required • estimate: 1 hour per beam and plane, allocate 2 hours to aperture measurement • may not have enough time in this MD for all planes and beams W. Hofle LSWG - 16. August 2011

  4. Preparations so far (D. Valuch, M. Jaussi, D. Jacquet) white noise deployed on 1 damper, ready to test (need to test before MD) band limiting under test a) low-pass b) band-pass band limitation will be used for loss maps  better use of available power gating implemented on FPGA  software interface to be finished (testing !) (gating is similar to abort gap cleaning, i.e. a “copy”) W. Hofle LSWG - 16. August 2011

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