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Reliability assessment for new materials: Generation and activation of electrical defects in high-k gate stacks. Gennadi Bersuker. Dielectric degradation: multilayer gate stack. - Defect location : in high-k or IL? Defect origin : intrinsic or process-related?

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Gennadi bersuker

Reliability assessment for new materials: Generation and activation of electrical defects in high-k gate stacks

Gennadi Bersuker


Dielectric degradation multilayer gate stack

Dielectric degradation: multilayer gate stack

  • - Defect location: in high-k or IL?

  • Defect origin: intrinsic or

  • process-related?

  • Defect generation mechanism:

  • stress condition-dependent or

  • ‘universal’?


Gennadi bersuker

  • Defects in interfacial SiO2

    Process-related High-k-induced:

    O-vacancies & Hf impurities

  • Defects in high-k

    As-grown: O-vacancies

    Stress generated – at high stress biases

    Polarons

  • Characterization

    Combining electrical and physical techniques, and modeling


Silc evolution for monitoring breakdown

SILC evolution for monitoring breakdown

TiN/ 3nm HfO2/2.1nm SiO2

CVS 4.6V

Stress-induced leakage current reflects on the formation of percolation path

G.B., IRPS 2007


Probing sio 2 traps

Probing SiO2 traps

SILC

Charge Pumping

Since CP probes IL, similar CP and SILC growth rates for each dielectric stack points to the same contributing defects in IL


Effect of stress voltage on reliability assessments

1.1nm SiO2/ 3nm HfO2

Vstress = 2.4 V

Vstress = 4.1 V

Effect of stress voltage on reliability assessments

Low voltage

High voltage

  • Low voltage: activation of precursor defects in IL

  • High voltage: defect generation in IL


Gennadi bersuker

Si L2,3-edge EELS

Si

Si

Solid – as-deposited

Dashed – after 1000C anneal

SiO2

Si/SiO2

HfO2

SiO2

SiO2/HfO2

High-k–induced O vacancies in SiO2 IL: EELS

K. van Benthem, Pennycook

Higher O deficiency higher density of precursor defects (Si-Si)  converted by stress into electron traps Si-

G.B., JAP 2006


Metal high k induced o defects in sio 2 esr

Metal/high-k-induced O defects in SiO2: ESR

Metal/high-k process significantly enhances E’ center density in interfacial SiO2 layer

3nm HfO2/1nm SiO2/TiN+ 1000C PDA

3nm HfO2/1nm SiO2 +1000C PDA

3nm HfO2/1nm SiO2

J. Ryan et al., APL 2007


Metal high k induced o defects in sio 2 esr1

Metal/high-k-induced O defects in SiO2: ESR

SiO2 (20Å)+ HfO2 (30Å)/TiN + 1000ºC/10s

SiO2 (10Å)+HfO2 (30Å)/TiN + 1000ºC/10s

J. Ryan et al.

High-k-induced (process-related) generation of E’ centers is much more effective in thinner SiO2 layers

12


Fast interface trap generation dciv

High-k

DDit

DVt

Fast interface trap generation: DCIV

DCIV measurements

SiO2

Neugroschel, IEDM 2006

High-k devices show strong initial increase of both trapped charges and interface traps


Gennadi bersuker

Hf defects in IL: spin dependent recombination

HfO2/SiO2

SiO2

Lenahan, IRW 2006

Fast transient defect generation might be associated with Hf atoms in interfacial SiO2 layer


Fast degradation hf in sio 2 il

Fast degradation: Hf in SiO2 IL

SiO2

Amorphous layers

Si

HfO2

SiO2

Si

“Regular” structure

Hf

G.B., JAP 2006

Hf can diffuse through voids in SiO2

S. Rashkeev, INFOS 2005


Long term instability defects in sio 2

Long-term instability: defects in SiO2

Threshold voltage

Interface states

Neugroschel, IEDM 2006

Similar degradation rates in high-k stack and control SiO2 same mechanism


Defect generation in high k film

200

200

180

180

160

160

140

140

Vstress = 5 V

120

120

100

100

80

80

60

60

40

40

20

20

0

0

-0.5

-0.5

0.5

0.5

1.5

1.5

2.5

2.5

3.5

3.5

4.5

4.5

5.5

5.5

Stress time x1000 (sec)

Stress time x1000 (sec)

Defect generation in high-k film

Low Vg:

mostly reversible

High Vg:

w/ continues degradation

1.1nm SiO2/ 3 nm HfO2

Vstress= 2.4 V

180

140

DVt (mV)

100

60

after discharge

after discharge

20

after discharge

0.5

1.5

2.5

3.5

4.5

5.5

Stress time x1000 (sec)

  • Low stress voltage: reversible filling of pre-existing traps

  • High voltage: trap generation


Defect generation in high k pulse measurements

Gate

Gate

High

-

k

Defect generation in high-k: pulse measurements

Defect generation at as-grown defect precursors


Trapping in amorphous high k

Trapping in amorphous high-k

J. Gavartin, ECS 2006

Injected electron can trap via self-localization (polaron formation)  No defects needed to charge high-k film


Summary

Summary

  • Interfacial SiO2 layer:

  • - Low bias stress: trap generation at as-processed precursor defects (O vacancies/Hf atoms) induced by high-k dielectric

  • - High bias stress: new “conventional” defects

  • High-k film:

  • - Low bias stress:instability due to reversible electron trapping on as-processed defects (O-vacancies) or polaron formation(?)

  • - High bias stress:defect generation at as-processed precursors: Defect nature? Mechanism?


Specifics of metal electrode high k dielectric gate stacks

Specifics of metal electrode/high-k dielectric gate stacks

  • Multi-layer dielectric stacks

    Interfacial SiO2, high-k dielectric, metal/high-k interface

  • Ultra-short characteristic times

    Transient charging/discharging (relaxation) effects

  • High density of pre-existing defects

    O vacancies, under-coordinated metal and Si atoms

    Question applicability of SiO2 test methodologies


New materials reliability issues

New Materials Reliability Issues

  • Reversible parameter instability – sensitive to measurement times; can be partially addressed by design

  • Stress-dependent degradation mechanisms- test close to use conditions

  • Strong process-dependent characteristics– reliability assessment requires extensive set of gate stacks of variety of compositions/processing


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