Le linac modulator update
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LE Linac Modulator Update. Trevor Butler April 3 rd , 2013 Data from: Dan Wolff, Howie Pfeffer, & Jim Biggs (EE Support) Mark Kemp & Tony Beukers (SLAC). Fermilab EE Support Modulator. Data by Dan Wolff, Howie Pfeffer, & Jim Biggs. Main IGBT Switching Device.

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Le linac modulator update

LE Linac Modulator Update

Trevor Butler

April 3rd, 2013

Data from:

Dan Wolff, Howie Pfeffer, & Jim Biggs (EE Support)

Mark Kemp & Tony Beukers (SLAC)


Fermilab ee support modulator

Fermilab EE Support Modulator

Data by Dan Wolff, Howie Pfeffer, & Jim Biggs


Main igbt switching device

Main IGBTSwitching Device

  • Infineon Medium Power IGBT

  • Part Number FF300E17KE3

  • Rated for 1700 Volts and 300 Amps (600 Peak)

  • Uses EiceDRIVERTM Dual IGBT Driver Board (#2ED300C17-S) with Soft Shut Down feature for fault conditions

  • To speed up development time, the Evaluation board (#2ED300E17-SFO) was purchased

    • Uses Fiber Optic Interface to drive the switch direct or in half-bridge mode

    • Due to excessive cost of unit, these boards where drafted at Fermilab and fabricated

    • Boards currently being stuffed with components


Single cell modeling

Single cell modeling

Modeling to

include:

IGBT turn

on/off times.

Diode reverse

current (Qrr)


Single cell model switch voltage

Single cell model – switch voltage

Switch transient voltage


Voltage transients test setup

Voltage Transients Test Setup


Simple spice model

Simple Spice Model


Simple spice model1

Simple Spice Model


Simple spice model2

Simple Spice Model


Voltage transients test setup1

Voltage Transients Test Setup

  • IGBT Collector Voltage set to 900 V

  • Current set to 350 Amps

  • Taken with 5.6 F Snubber Capacitor across IGBT

  • Output Voltage pulse undershoots by ~ 200 Volts

  • Total VCE swing limited to 1100 - 1200 Volts

  • IGBT has VCE rating 1700 Volts


Short circuit test setup

Short Circuit Test Setup


Short circuit spice model

Short CircuitSpice Model


Simple spice model3

Simple Spice Model


Short circuit test setup1

Short Circuit Test Setup

  • The SSD “Soft Shut Down“ is used to softly shut down the IGBT if a fault occurs.

  • This is useful in order to avoid destruction of the IGBT due to high voltage overshoots during turnoff.

  • The SSD will reduce the turn-off di/dtand the voltage overshoot during fault conditions.

  • This test confirmed that the switch will shutdown safety during spark

Short Circuit Current

100Amps/Volt

Short Circuit Current

100Amps/Volt

VGE

Voltage Pulse on

IGBT Gate & Emitter

Voltage Pulse on

IGBT Gate & Emitter


Simple spice model with 0 5 ohm resistance for igbt

Simple Spice Modelwith 0.5 Ohm resistance for IGBT


Mechanical layout of igbt snubber and main storage capacitor

Mechanical Layout of IGBT, Snubber, and Main Storage Capacitor

  • Switching speed is an important design criteria.

  • Stripline is use to minimize inductance between all three devices

  • Snubber cap is designed to be bolted directly on the IGBT terminals


Status report

Status Report

  • Individual Switch testing accomplished and passed.

    • Switching Transient

    • Short Circuit Response Tests.

  • EE Support is continuing to work on the computer model of the system with emphasis on controlling the waveform an the individual cells

  • Single cell computer modeling has been developed

    • Device voltage, Diode currents, and regulating cell requirements

  • Mechanical construction of two Marx Stages is complete

  • Building a total of 9 Marx Stages for testing

    • All of the parts have been delivered

    • Working on creating striplines, heatsinks, etc. for the remaining 7 units

    • Goal to have completed by May 2013


Status report1

Status Report

  • Designed the firing cards that will control the main switching elements. Currently being filled with components

  • Working on build a simple control architecture to fire the 9 cells for initial testing

    • Desire is to create any arbitrary wave shape

    • Have adjustable rise and fall time

    • Advanced controls, like would take place in the final design, will not be implemented

    • Test setup will be built with discrete logic based on comparators and the final design will incorporate PAL’s

  • Charging system ideas are being considered

  • Currently reviewing different types of control systems to use for the final design that can match the speed and resolution required

    • Need 14 bits at 20 MHz to achieve the amplitude resolution/stability and to achieve the desired 100 ns accuracy of beam timing


Slac modulator for fermilab

SLAC Modulator for Fermilab

Data by Mark Kemp & Tony Beukers


The slac p2 marx

The SLAC P2 Marx

  • The SLAC P2 MARX Modulator (-120 kV 140 amp 1.7ms)

  • 32 Marx cells charged in parallel by a -4 kV supply

  • Hardware development has ended.

  • Controls development continues

  • Development results from large modulator program for ILC

  • SLAC desires to utilize technology for additional applications


Goal of phase 2b study

Goal of Phase 2B Study

  • Modify two Marx cells and the test stand to accommodate the Fermi cell parameters.

  • Demonstrate the transient waveform characteristics at the single and two cell level.

  • Both Main Cells and Vernier Cells will be designed and tested.

  • Computer model to be update with actual results to create more realistic simulation


Test setup

Test Setup


Test setup1

Test Setup


Main cells

Main Cells

  • Typical Main Cells Voltage

    • 4 kV for Large Energy Storage Capacitor (350 F)

    • 1 kV for Smaller PWM Filter Capacitor (20F)

  • To limit the power, cells where tests up

    • 2.5 kV for Large Energy Storage Capacitor (350 F)

    • 0.8 kV for Smaller PWM Filter Capacitor (20 F)

  • Testing into a 25  load to run with higher currents while keeping the voltage low

  • This experimental data will be matched to the simulations, and adjustments will be made to the computer model, to better simulate the final system


Main cells v main storage 1400 v pwm filter 700 load voltage brown load current green

MAIN CELLS (Vmain storage=1400, Vpwm filter=700)Load Voltage (Brown) & Load Current (Green)

2 Main Cell – PWM out of phase – averaging

2 Main Cell - PWM in phase – no averaging

2 Main Cell – Staggered Turn-on

2 Main Cell – Synchronous Turn-ON


Main cells v main storage 2500 v pwm filter 800 load voltage brown load current green

MAIN CELLS (Vmain storage=2500, Vpwm filter=800)Load Voltage (Brown) & Load Current (Green)

2 Main Cell – PWM out of phase

2 Main Cell - PWM in phase - staggered

2 Main Cell - PWM in phase

152 Volts of Ripple

103.2 Volts of Ripple (68%)


Ripple reduction with running the marx cells out of phase

Ripple Reduction with running the Marx Cells out of phase

Going from 2 to 5 cells (Vernier) reduces ripple to 15%

Going from 2 to 10 cells (Main) reduces ripple to 2% !!!!


Vernier cells

Vernier Cells

  • Typical Main Cells Voltage

    • 4 kV for Large Energy Storage Capacitor (350 F)

    • 1 kV for Smaller PWM Filter Capacitor (20F)

  • To limit the power, cells where tests up

    • 2.8 kV for Large Energy Storage Capacitor (350 F)

    • 1kV for Smaller PWM Filter Capacitor (20 F)

  • Testing into both a 25  load and a 25  Load in series with a 200 H inductor, to act as a stiff current source, roughly approximating the type of load the 7835 presents

  • This experimental data will be matched to the simulations, and adjustments will be made to the computer model, to better simulate the final system


Vernier cells v main storage 1700 v pwm filter 700 load voltage brown load current green

VERNIER CELLS (Vmain storage=1700, Vpwm filter=700)Load Voltage (Brown) & Load Current (Green)

2 Vernier Cell – PWM out of phase – averaging

2 Vernier Cell - PWM in phase – averaging

25  Load

473.6 Volts of Ripple

73.6 Volts of Ripple (15%)


Main vernier cells v main storage 2800 v pwm filter 700 load voltage brown load current green

MAIN & VERNIER CELLS (Vmain storage=2800, Vpwm filter=700)Load Voltage (Brown) & Load Current (Green)

1 Main Cell & 1 Vernier Cell – NO PWM

2 Vernier Cells – NO PWM– synchronous

25  +

200 H

Load


2 vernier cell ramp down ramp up

2 Vernier Cell Ramp Down & Ramp Up

Vmain storage=1.3 kV & Vpwm storage cap= 1kV

Vmainstorage=2.3 kV & Vpwmstorage cap = 1kV


Lesson learned

Lesson Learned

  • Note that the data presented was just measured and more data will be taken and analyzed before final report is presented by SLAC

  • The two challenging specifications of ripple and slew rate need to be analyzed father using the 2 cell data to determine the effect on a full scale prototype

    • Slew Rate

      • With approximated 3kV/s per 2 cell, then 7.5kV/s could be obtained with all 5 cells firing simulation. (More if the cells would be run near 4kV)

      • This does not mean achieving .75kV/100ns is possible, or even3.75kV/0.5s

      • Instead, the best way to think about it Vernier Cells take 1-2 us to rise up

      • This result is a little less than the desired specification of 15kV /s

    • Ripple

      • Minimizing Ripple will require that all 5 vernier cells are used to fire the beam step no mater the size of the step, otherwise, the ripple of one stage is more than the desired specification

      • All Vernier cells will be fired 360/5 = 72 degrees

      • All Main Cells will be fired 360/10 = 36 degrees


Ripple repeatability

Ripple & Repeatability

  • The reduction in ripple from going from 2 stages to 5 stages in the vernier is a drop in 85%, and going up to 10 stages give a drop of 98%

    • 2 Vernier Stages = 74 VP-P

    • 5 Vernier Stages 74*.15=11.1 VP-P

    • 2 Main Stages = 103 VP-P

    • 10 Main Stages 103*.02=2.06 VP-P

  • The Ripple in the waveforms appears to be within specificationof 50 VP-P

  • Repeatability data will be presented for the ILC Marx P2 design

    • This data will be considered when estimating the repeatability data of the Marx F1 design

  • By adjusting the values on the snubber networks for both the main and vernier cells, there is a tradeoff between ripple and slew rate

  • It may be possible to increase slew rate at a sacrifice of ripple if desired. Once the data taken is incorporated back into the computer model, then simulations can be used to determine the tradeoffs between designs before a final modulator is built


Future study plans phase 2b

Future Study Plans (Phase 2B)

  • Validate new capacitors (Easy)

    • Need to life test new storage capacitors; can cost share with another project

  • Develop new gate drive (Easy)

    • Essentially just updating present PCB and removing some functionality used in the P2

  • Layout new snubber boards (Easy)

    • Straightforward

  • Test lab setup (Easy)

    • Need to prepare load and lab area

    • Could be put off until decision is made on whether to go forward with full design

  • Update cell mechanical layout (Easy , but material high cost)

    • Need to incorporate new IGBT, new snubbers, and new capacitors

    • Should keep overall same shape

  • Finalize Documentation Package (Easy)

  • Implement new safety relay design (Medium)

    • Need new layout

    • Implementation was troublesome in the P2


Future study plans phase 2b1

Future Study Plans (Phase 2B)

  • Finalize Enclosure design (Medium)

    • Fabrication would be outsourced

    • Vendors already identified and quotes obtained

    • Would need to finalize design

    • Not labor intensive

  • Develop and test new application manager hardware interface (Difficult and high material cost)

    • Hardware is fairly straightforward and many already validated DACs and ADCs can be re-used

    • Challenge is in communication and choice of interface

  • Prototype control software (Very Difficult)

    • Can be substantially re-used from P2

    • New aspect is the reference originating from outside

    • The beam step trigger instantaneously triggering the vernier

    • How to implement into the current controls

    • Designed to take over LLRF control, which took years to develop


Next steps

Next Steps

  • I will continue working to document the present operation of the modulator and LLRF system to determine best way to control the Marx Modulator under the constraint of the present beam operational mode

  • Mark Kemp from SLAC will continue collecting data and present finding at Fermilab at the end of April (perhaps April 25-30)

  • Need to decide what to do next

    • Use remaining funds ($10k) for more studies

    • Preform more computer modeling of data to determine what circuit parameters (snubber filters, etc.) could be changed to optimize performance (? Maybe $50-100k – we where never given a price to just this work)

    • Using the changed determine from the simulation data preform, make changes to the 2 Main and 2 Vernier cells and retest (~75k of less)

    • Start next Phase (2B) where we could study the above mentioned a events (~$240k)

    • Purchase entire prototype design ($1.38M)

      • This option is not preferred since we should consider the control system more important than building cells, since more optimization may still be needed for cells


Le linac modulator update

End


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