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TI Enables Beyond3G Cellular Infrastructure With New Products

TI Enables Beyond3G Cellular Infrastructure With New Products. Embargo Date – February 4, 2008 Ramesh Kumar Marketing Director, Communications Infrastructure Group. Data-Intensive Applications Drive Infrastructure Complexity. 100. Video conferencing, VoD Interactive gaming Wireless VPNs,

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TI Enables Beyond3G Cellular Infrastructure With New Products

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  1. TI Enables Beyond3G Cellular Infrastructure With New Products Embargo Date – February 4, 2008 Ramesh Kumar Marketing Director, Communications Infrastructure Group

  2. Data-Intensive Applications Drive Infrastructure Complexity 100 Video conferencing, VoD Interactive gaming Wireless VPNs, Streaming video INTERACTIVITY “4G” Streaming audio Streaming video clips Enterprise Apps (Word, Excel, Outlook) Complex games Robust Web Browsing 10 STREAMING HSDPA, HSUPA CDMA2000 1x-EV-DO R. A CDMA2000 1x-EVDV 1 Peak Data Transmission (Mbps) Multimedia messaging Video clips, Web browsing Games MULTIMEDIA CDMA2000 1x-EV-DO Text E-mailing Ring Tones Simple games W-CDMA 0.1 E-MAIL SMS, IMS EDGE, CDMA2000-1x 0.01 GPRS, cdma2000 GSM Source : iSuppli 0.001 • Deployment of 3G worldwide is the primary driving force • Operators see source of new revenue and increased ARPU around broadband-speed data services • Quality, capacity and latency issues remain

  3. Standards Migration + Lack of Convergence = Challenging Landscape for Base Station OEMs 2H08 – HSPA+ Phase 1 deployment begins 2H09 – HSPA+ Phase 2 deployment begins 2H10 - 1st Network Deployments begin 1H08 – HSUPA deployment begins 2H05 – HSDPA deployment begins 4Q07 – 1st LTE Prototypes Systems Available 4Q08 – LTE Trials Begin 3Q06 – Early LTE development begins 1H11 - Commercial Service Availability 4Q09 – 1st LTE production systems available 2H06 - 802.16e certification begins 4Q05 802.16e Phy standard ratification expected 4Q07 - Sprint begins WiMAX deployment 2H2008 Integrated chipsets for PCs expected (Intel) 2Q2007 802.16e (WiMAX Mobility) certified production shipments 2006 2007 2008 2009 2010 2011 2H2009 Evolved EDGE Deployments Begin 2H2008 Evolved EDGE Trials Begin

  4. TCI6484: The Hardest Working DSP Available C64x+™Core RSA Timers PLL Enhanced DM L1 D MEM Boot ROM L1 P MEM TCP2 VCP2 TCP2 L2 MEM EDMA 3.0 with Switch Fabric HPI SRIO UTOPIA I2C McBSP SGMII EMIF 64 GPIO DDR-2 Key Features: • Support for MAC and PHY layers on a single platform eliminates the need for a RISC co-processor • Enhanced memory and cache performance for efficient MAC-layer processing: -- Increased L2 cache size to 1 megagbyte (MB); total L2 memory of 2 MB -- Increased 32-bit double data rate (DDR) memory speed to 667 MHz • Increased symbol rate processing with up to 34 megabits per second (Mbps) of performance via dual Turbo Co-Processors (TCP2) Programmable platform supports multiple standards: GSM-EDGE, EDGE Evolution, ,TD-SCDMA, WCDMA, HSPA, HSPA+, LTE, WiMAX • Scalable across multiple form-factors: macro, micro and pico base stations • Full selection of peripherals: Serial Rapid IO, sGMII for 10/100/1000 Ethernet, HPI, I2C, two McBSP ports, UTOPIA

  5. Optimized Single Core Partitioning Delivers More Performance Speed Enhancements • Speed increased from 533 to 667Mhz for DDR2 • Overall improvement in DDR2 access, latency and speed • Support faster access to off chip memory • Improves overall performance and access for off chip memory Memory system improvements • 400% larger cache memory • Max L2 Cache size increased by 4x - 1024M vs 256K for TCI6482 Maximized Throughput • Two independent Turbo coprocessors (TCP2), separately connected to switch fabric • Provides ~34Mbps UL throughput • Multiple 11.2 Mbps HSUPA+ sectorson a single device • 10MHz LTE without MIMO • Sufficient TCP decoding for early LTE Symbol rate 2MB L2 Memory Curie 1024K Cache 1024K 1792K Himalaya 256K Cache “New” Cache Memory 256K Cache 1024K Cache

  6. Scheduler Benchmark Data Proves Performance Enhancements Total cycles for sending/receiving 1M packets 10% Cache Pre- Loading TCI6484 Est.TCI6484 TCI6482 Silicon Diff Simulator Silicon * Silicon 32k 2.80E+09 2.69E+09 2.95E+09 8.88% 64k 2.69E+09 2.58E+09 2.90E+09 10.95% 128k 2.55E+09 2.45E+09 2.79E+09 12.26% 256k 2.43E+09 2.33E+09 2.75E+09 15.17% 512k 2.36E+09 2.27E+09 17.61% 1024k 2.31E+09 2.22E+09 19.36% Total cycles for sending/receiving 1M packets 90% Cache Pre- Loading TCI6484 Est.TCI6484 TCI6482 Silicon Diff Simulator Silicon * Silicon 32k 2.92E+09 2.80E+09 3.10E+09 9.57% 64k 2.83E+09 2.72E+09 3.05E+09 10.92% 128k 2.68E+09 2.57E+09 2.96E+09 13.08% 256k 2.57E+09 2.47E+09 2.83E+09 12.82% 512k 2.50E+09 2.40E+09 15.19% 1024k 2.38E+09 2.28E+09 19.27% • Scheduler test • Cycle count to send/receive 1M packets • Tested at various cache sizes from 32k to 1024k • TCI6482 has 256K Cache • TCI6484 will have 1024K Cache • Data collected from both actual Si and simulation • Two test cases studies. 10% and 90% cache pre-loaded • Results • TCI6484 offers up to 19% improvement over TCI6482 on scheduler functions * TCI6484 Silicon estimate based upon a historical 4% improvement from simulator to actual silicon device.

  7. TCP/VCP Enhancements Support More Channels/Carriers Per Device

  8. Interface-Specific Software Libraries Reduce Customers’ Development Time by 50% TCI6488 TCI6487 TCI6482 TCI6484 DSP DSP DSP DSP Single Core WCDMA-HSPA HSPA+ Software Libraries GSM-EDGE Software Libraries Solution Analysis & System Partition Multicore LTE Software Libraries WiMAX Software Libraries DEVELOPMENT ENVIRONMENT

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