Lecture 13: Floating Point Instructions, Program Control

1. Lecture 13:Floating Point Instructions,Program Control Soon Tee Teoh CS 147

2. RISC or CISC • 2 different types of ISA, different “philosophy”, trade-offs • RISC (Reduced Instruction Set Computers) • CISC (Complex Instruction Set Computers) • RISC: • Memory accesses restricted to load/store, data manipulation are register-to-register • Limited number of addressing modes • All instructions same length • Instructions are elementary • CISC: • Memory access directly available to most instructions • Many different addressing modes • Instructions of varying lengths • Some instructions simple, some complex • Many ISAs are between RISC and CISC

3. Conditional Branch Instructions • The PC (or Program Counter) is a register that contains the memory address of the current instruction being executed. • Normally PC is simply incremented, unless branch or jump • Example: “if-else” statements often translated to conditional branch • Allows change in the next instruction to be loaded Example: Instruction format from Table 10-8, page 454 ADD R5 R3 R1 BRN R5 3 SUB R2 R2 R5 SUB R1 R2 R1 LD R5 R2 If the contents of R5 is less than 0, then skip the next two instructions and go straight to the LD instruction. Note: conditional branches usually not too far away, so we can use immediate relative addressing.

4. Status Bits for Branch Control Function Unit Branch Control V C N Z V C N Z PL JB BC From part of Figure 10-15, page 457 V, C, N and Z are the status bits used by the branch control. They come out of the function unit. V: Overflow (set to 1 if overflow has occurred in the ALU, 0 otherwise) C: Carry (the last carry bit) N: Negative (set to 1 if the result of the ALU operation is negative) Z: Zero (set to 1 if the result of the ALU operation is zero) Exercise: Can you draw the circuit to output these status bits from the ALU?

5. Some Possible Branch Instructions For the instructions on this and the next slide, assume that the operands in the registers are treated as signed integers in 2’s complement representation. Branch Instruction Mnemonic Format Action Branch if zero BZ RA, AD If (R[SA]==0) PC PC + se AD Branch if not zero BNZ RA, AD If (R[SA]!=0) PC PC + se AD Branch if negative BN RA, AD If (R[SA]<0) PC PC + se AD For above instructions, set FS to 0000 so that the output of the Function Unit is its input A (see Table 10-4, page 443). Then, the branch conditions are: Branch Instruction Mnemonic Branch Condition Branch if zero BZ Z == 1 Branch if not zero BNZ Z == 0 Branch if negative BN N == 1 Adapted from Table 11-8, page 514

6. Some Other Possible Branch Instructions Branch Instruction Mnemonic Format Action Branch if greater BG RA, RB, AD If (R[SA]>R[SB]) PC PC + se AD Branch if greater or equal BGE RA, RB, AD If (R[SA]>=R[SB]) PC PC + se AD Branch if less BL RA, RB, AD If (R[SA]<R[SB]) PC PC + se AD Branch if less or equal BLE RA, RB, AD If (R[SA]<=R[SB]) PC PC + se AD For above instructions, set FS to 0101 so that the output of the Function Unit is A-B (see Table 10-4, page 443). Then, the branch conditions are: Branch Instruction Mnemonic Branch Condition Branch if greater BG ( N + V ) + Z == 0 Branch if greater or equal BGE N + V == 0 Branch if less BL N + V == 1 Branch if less or equal BLE ( N + V ) + Z == 1 Adapted from Table 11-10, page 515

7. Examine BL in more detail • BL means branch if A is less than B. • We execute A – B in the Function Unit. • If the result is negative, we should branch. • However, if the operation has an overflow, that means that the true value of A – B is actually the opposite sign from the output F of the Function Unit. N V True value of A-B Branch or not 0 0 Positive Don’t branch 0 1 Negative Branch 1 0 Negative Branch 1 1 Positive Don’t branch Summary, for BL, branch if N xor V is 1. Otherwise, don’t branch

8. Jump Instructions • Unconditionally sets PC to be instruction-specified value. • Usually in register-indirect mode. • New PC gets the specified value rather than PC + 1. From Table 10-8, page 454: JMP RA means PC gets the contents of RA

9. Procedure Call and Return • Calling a sub-routine • Transfer PC to the beginning of callee • Need to save the address of the caller (the return address) • The return address is saved in a stack • Using a stack enables nested procedure calls Calling a sub-routine: SP SP – 1 M[SP] PC PC effective address of sub-routine Returning from procedure call: PC M[SP] SP SP + 1 Typically, Instruction Set Architectures have a JML (Jump and Link) instruction that is used for making procedure call, and a JMR (Jump Register) instruction to return from a procedure call. See Table 12-1, page 540.

10. How does a Stack work? • Stack is a part of the memory • A register $SP keeps the pointer (address) of the top of the stack • In Push operation, $SP is decremented, and the data to be put into the top of the stack is written into the memory at the location specified by the new $SP • In Pop operation, the contents of the memory at location specified by $SP is read, and $SP is incremented. Stack grows 100 101 102 103 104 100 101 102 103 104 000011 101011 111000 001100 101011 111000 001100 Say $SP is 102. After PUSH 000011, we get Now $SP contains 000011

11. How does a Stack work? • A POP example Say, the top of the stack is currently at 101. In other words, register $SP contains 101. Now, register $SP contains 102. Register R1 contains 000011. 100 101 102 103 104 100 101 102 103 104 Top of stack 000011 101011 111000 001100 101011 111000 001100 Top of stack Execute instruction “POP R1”

12. Program Interrupt • Interrupt: depart from normal program sequence, also called “exception” • Triggered not by instruction in the program itself • Types of interrupts: • External interrupts: for example, from timing devices, I/O devices • Internal interrupts: traps (invalid or erroneous use of an instruction or data), eg. overflow, divide by zero, protection violation • Software interrupt: Generate an interrupt explicitly with an instruction • Processing an interrupt: Similar to procedure call and return: save registers and PC, give PC to the interrupt handler, and return. Interrupt handler may disable further interrupts while it is working.

13. Floating Point Representation • Suppose we have 32-bit registers. • Suppose we use 1 bit for the sign, 23 bits for the fraction, and 8 bits for the exponent. • Suppose the sign is 0, the fraction is 11010000000000000000000, and the exponent is 00000011 • The number is (0.1101)2 x 23 = (110.1)2 = (6.5)10

14. Floating Point Additions • To add two numbers with different exponents, shift right the fraction part of the number with the smaller exponent • Now the fractions are lined up. Then add. • The exponent of the sum is the bigger exponent

15. IEEE Standard: Normalization and Biased Exponent • A normalized floating point number has 1 in the first position, eg. 0.100101 is normalized, 0.0010101011 is not. • For biased exponent, we add a bias to the exponent • In IEEE 32-bit floating point standard, we have 1 bit for the sign, 8 bits for the exponent, and 23 bits for the fraction. Note that the fraction is automatically normalized. • The effective number is: (-1)s2e-127 x (1.f) 1 8 23 s e f

16. IEEE StandardFloating Point Example 1 0 1 0 1 1 0 1 00 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Treat this as an unsigned number 010110102 = 90 The number is (-1)12(90-127)(1.01110010000000000000000)2 = -1 x 2-37 x (2 + 1/4 + 1/8 + 1/16 + 1/128)

17. Floating Point Arithmetic • Floating point addition • To add two floating point numbers, shift the fraction part of the number with the smaller exponent to the right by the number of bits equal to the difference between the two exponents. • Then add the fraction part. • Then re-normalize if necessary. • Floating point multiplication • Add the exponent parts and multiply the fraction parts