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SET Fault Tolerant Combinational Circuits Based on Majority Logic

SET Fault Tolerant Combinational Circuits Based on Majority Logic. Álisson Michels Lorenzo Petroli Carlos Lisbôa Fernanda Kastendsmidt Luigi Carro. When a single fault occurs in the voter circuit, the voter output may be wrong. V O T E R. Module 1.

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SET Fault Tolerant Combinational Circuits Based on Majority Logic

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  1. SET Fault Tolerant Combinational Circuits Based on Majority Logic Álisson Michels Lorenzo Petroli Carlos Lisbôa Fernanda Kastendsmidt Luigi Carro

  2. When a single fault occurs in the voter circuit, the voter output may be wrong V O T E R Module 1 correct output V O T E R Module 1 wrong output Module 2 correct output ? correct output Module 2 correct output wrong output Module 3 correct output Module 3 wrong output What is Wrong with TMR ? • TMR does not protect against two faults affecting different modules

  3. transient pulse model: double exponential • injection of faults • no effect on voter output Fault-tolerant analog voter

  4. majority(a, b, 0) = a.b + a.0 + b.0 = a.b (AND gate) • majority(a, b, 1) = a.b + a.1 + b.1 = a.b + a + b = a + b (OR gate) • the analog comparator can be used as a fault-tolerant inverter AND gate OR gate inverter Use of majority gates in AOI logic

  5. Sample implementation: full adder Classic TMR implementation: - 3 standard AOI full adder modules - 1 digital voter per output bit Proposed solution: - single full adder module - majority gates used to implement AND/OR functions - analog comparators used to implement majority gates and inverters

  6. Area Comparison(32 nm technology) The proposed solution brings a 36% reduction in area, when compared to the classic TMR implementation

  7. Thank You ! For more details, come and see the poster ! Contact: calisboa@inf.ufrgs.br

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