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Research on Reconfigurable Computing Using Impulse C. Carmen Li Shen Mentor: Dr. Russell Duren February 1, 2008. Presentation Overview. Background Information Introduction Impulse C Current Work Conclusion & Future Research Questions. Background Information. Reconfigurable computing

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research on reconfigurable computing using impulse c

Research on Reconfigurable Computing Using Impulse C

Carmen Li Shen

Mentor: Dr. Russell Duren

February 1, 2008

presentation overview
Presentation Overview
  • Background Information
  • Introduction
  • Impulse C
  • Current Work
  • Conclusion & Future Research
  • Questions
background information
Background Information
  • Reconfigurable computing
  • Field Programmable Gate Arrays (FPGAs)
  • Hardware Description Languages (HDLs):
    • Verilog
    • VHDL
  • C++ and C-based software programming languages:
    • System C
    • Impulse C
reconfigurable computing
Reconfigurable Computing
  • Employing programmable logic devices where the hardware-based logic itself is being modified
  • Reprogram hardware vs. modifying the program that use a fixed hardware configuration
  • Programming FPGAs vs. Von Neumann Computers
    • Reconnecting internal gates to modify the hardware
    • The hw is optimized to perform one function
    • Vs. changing software running on a processor

Image provided by: http://www.fhpca.org/images/Maxwell_small.jpg

field programmable gate array

μProc

RAM

Custom Circuitry

I/O

Field Programmable Gate Array
  • Microprocessor
  • User I/O
  • TCP/IP
  • Control & Test Benches
  • Custom Circuitry
  • Complex calculations
  • (e.g. NN, DSP)

FPGA

Image provided by: http://www.nuhorizons.com/products/NewProducts/POQ13/xilinx.html

src 6e hardware architecture

μP Board

MAP

Intel® μP

Intel® μP

315/195 MB/s

Controller

L2

L2

6x 800 MB/s

MIOC

On-Board Memory (24 MB)

6x 800 MB/s

SNAP

PCI

Common

Memory

Chain Port 800 MB/s

Chain Port 800 MB/s

FPGA

FPGA

SRC-6e Hardware Architecture
  • Features:
  • 2 XC2V6000 FPGA
  • 288 MACs , BRAMs
  • 2 Pentium 3
  • 24MB of SRAM
  • 64-bit ports
  • Cost ~ $300,000
xup virtex ii pro platform
XUP Virtex II Pro Platform

Features:

  • XC2VP30 FPGA
  • 136 MACs , BRAMs
  • 2 PowerPC
  • 256 MB DDR SDRAM
  • 10/100 Ethernet
  • SATA connectors
  • Serial, JTAG, audio, video, USB, etc. ports
  • Cost ~ $300 - $1,600
research

Willis Troy

Dr. Eisenbarth

Dr. Duren

Research
  • Our research:
    • Impulse C
    • Multiple FPGAs
  • Methodology:
    • Implement a calculation-intensive program
    • Compare to previous work and the SRC-6e

Image provided by: http://www.gamedev.net/reference/programming/features/vehiclenn/figure1.png

neural network

Hidden Layers

Neural Network
  • Trained network
  • 27 inputs
  • 3 Hidden Layers

(with 40 50 & 70 nodes)

  • 1200 outputs
  • Additions, multiplication, squashing
impulse c
Impulse C
  • C-language development tool
  • FPGA-accelerated computing
  • Function library for parallel programming fully compatible with ANSI C
  • CoDeveloper Tools
  • Mixed software/hardware
  • Cost ~ 3,000

Image provided by: http://www.ilink.co.jp/public/img/product/impulse/imp-c/flow.jpg

impulse c11
Impulse C
  • Data movement via streams and shared memory
  • Shared memory tradeoff: large but slow
    • Memory accessed via OPB bus (opb2plb bridge)
  • Floating point implementation supported
  • Customized instructions
    • xil_printf (2,953 bytes) vs printf (51,788 bytes)
    • Does not support type real numbers (floating point) or long-long types (64 bit)
impulse c to bitstream

Build Simulation Executable

Launch ANSI-C Simulation Executable

select a platform target

Generate HDL

Xilinx Platform Studio Project (EDK)

Export Generated Hardware

Export Generated Software

Xilinx Platform Studio Project (EDK)

Impulse C to Bitstream

C

VHDL

Bitstream

current implementation

Inputs & 3 Hidden Layers

600 Output Nodes

600 Output Nodes

Current Implementation

Neural Network

big neuralnet sw c
Big_NeuralNet_sw.c

Software Processes

Memory Object

big neuralnet hw c
Big_NeuralNet_hw.c

Hardware Process

Configuration Function

sigmoid function
Sigmoid function

y(x) = -y0”*(x – x0)2 + y0’*(x – x0) + y0

projects comparison
Projects Comparison

Similarities

  • Reconfigurable Computing
  • Neural Network and Weights
  • FPGAs

Differences

  • Implementation using VHDL vs. C
  • Fixed point vs. Floating point
  • Platforms / Architectures
conclusion future work
Conclusion & Future Work
  • Reconfigurable Computing
  • SRC-6e vs. XUP boards architectures
  • NN Calculations & Timing Results
  • Explore different levels of parallelism across multiple FPGA boards using multiple communication schemes
  • Ethernet, MPI, SATA Interfaces
  • RC cluster of Virtex II PRO

Willis Troy

Dr. Eisenbarth

Dr. Duren

acknowledgements
Acknowledgements
  • Dr. Russell Duren
  • Dr. Steven Eisenbarth
  • Willis Troy
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