Module 4:Metrics & Methodology Topic 4: Recovered Clock Timing. OGI EE564 Howard Heck. Where Are We? . Introduction Transmission Line Basics Analysis Tools Metrics & Methodology Synchronous Timing Signal Quality Source Synchronous Timing Recovered Clock Timing Design Methodology
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Module 4:Metrics & MethodologyTopic 4: Recovered Clock Timing
OGI EE564
Howard Heck
Section 4.4
Section 4.4
2 Problems of interest:
Section 4.4
Section 4.4
Section 4.4
DCLK
T
CO
Data @ A
T
f
T
flight
Data @ B
90°
RCLK
Section 4.4
T
(
DCLK)
pushout
DCLK
T
=T
+T
CO,max
co
co,pushout
Data @ A
T
=T
+ T
flight,max
flight
flight,pushout
Data @ B
RCLK
90°  (T
+ T
)
flight,pushout
CO,pushout
T
(
RCLK)
 T
(RCLK)  T
(DCLK)
pullin
pullin
pushout
Section 4.4
T
(
DCLK)
pullin
DCLK
T
= T
 T
CO,min
CO
CO,pullin
Data @ A
T
= T

T
flight,min
flight
flight,pullin
Data @ B
RCLK
90°  (T
+ T
)
flight,pullin
CO,pullin
T
(
RCLK,)
 T
(DCLK,)  T
(RCLK)
pushout
pullin
pushout
Section 4.4
Section 4.4
Section 4.4
Section 4.4
Section 4.4
Section 4.4
Section 4.4
Section 4.4
Section 4.4
Hold Requirement
Hold side margin
Setup side Margin
Setup Requirement
Cycles(N)
N=1
N=P
N=2M
N=M
High Frequency
Interconnect Noise
Low frequency drift between Dclk and Rclk
Section 4.4
[8.3.4]
Section 4.4
[8.3.5]
Phase difference, TDf is:
[8.3.6]
Tferror is the phase error at calibration (N=1).
Section 4.4
[8.3.7]
Section 4.4
[8.3.7]
[8.3.8]
[8.3.9]
[8.3.10]
Section 4.4
[8.3.11]
Section 4.4
Maximum data signal pushout w.r.t. refCLK over M cycles.
[8.3.12]
Minimum pullin of RCLK w.r.t. refCLK over M cycles.
[8.3.13]
Maximum flight time variation over M cycles.
[8.3.14]
Minimum phase relationship between data edge at the receiver input and RCLK..
[8.3.15]
[8.3.16]
Section 4.4
[8.3.17]
Section 4.4
[8.3.17]
[8.3.18]
[8.3.19]
[8.3.9]
Section 4.4
[8.3.18]
[8.3.20]
Section 4.4
[8.3.20]
Minimum data signal pullin w.r.t. refCLK over M+1 cycles.
[8.3.21]
Maximum pushout of RCLK w.r.t. refCLK over M cycles.
[8.3.22]
Minimum flight time variation over M+1 cycles.
[8.3.23]
Maximum phase relationship between data edge at the receiver input and RCLK..
[8.3.24]
Section 4.4
[8.3.25]
Section 4.4