Memory Management. 4.1 Basic memory management 4.2 Swapping 4.3 Virtual memory 4.4 Page replacement algorithms 4.5 Modeling page replacement algorithms 4.6 Design issues for paging systems 4.7 Implementation issues 4.8 Segmentation. Chapter 4. Memory Management.
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4.1 Basic memory management
4.3 Virtual memory
4.4 Page replacement algorithms
4.5 Modeling page replacement algorithms
4.6 Design issues for paging systems
4.7 Implementation issues
Three simple ways of organizing memory
- an operating system with one user process
CPU utilization = 1 - pn
where there are n processes in memory and each process spends a fraction p of its time waiting for I/O.
A computer has 32 MB. The OS takes 16 MB. Each process takes 4 MB. 80 percent of time is waiting for I/O. The CPU utilization is 1 – 0.84 = 60%. If 16 MB is added, then the utilization is 1 – 0.88 = 83%.
CPU utilization as a function of number of processes in memory
Degree of multiprogramming
Memory allocation changes as
Shaded regions are unused memory
Four neighbor combinations for the terminating process X
The position and function of the MMU
The relation betweenvirtual addressesand physical memory addres-ses given bypage table
Virtual page # 12-bit offset
32-bit address with 4k page size, 12-bit offset
20 bits for virtual page number
1 million entries!
Internal operation of MMU with 16 4 KB pages
where p1 is an index into the outer page table, and p2 is the displacement within the page of the outer page table.
0 = program text
1 = program data
1023 = stack
Second-level page tables
Typical page table entry
A TLB to speed up paging
EAT = (t + ) + (1 – ) (2t + )
= t + + 2t + - 2t -
= (2 – )t +
EAT = 0.8 x 120 + 0.2 x (200 + 20) = 140 ns.
Comparison of a traditional page table with an inverted page table
Class 0: not referenced, not modified
Class 1: not referenced, modified
Class 2: referenced, not modified
Class 3: referenced, modified
if R = 0 evict the page
if R = 1 set R = 0 and put page at end (back) of list. The page is treated like a newly loaded page.
(i) Set row K to all 1s.
(ii) Set column K to all 0s.
LRU using a matrix – pages referenced in order 0,1,2,3,2,1,0,3,2,3
Example: 10,000 instruction
The working set algorithm
Operation of the WSClock algorithm
Page fault rate as a function of the number of page frames assigned
Small page size
page table space
Two processes sharing same program sharing its page table
Four times when OS involved with paging
An instruction causing a page fault
(a) Paging to static swap area
(b) Backing up pages dynamically
Page fault handling with an external pager
Allows each table to grow or shrink, independently
Comparison of paging and segmentation
(a)-(d) Development of checkerboarding
(e) Removal of the checkerboarding by compaction
page number page offset
m – n n
Where p is an index to the page table and d is the displacement within the page.
A 34-bit MULTICS virtual address
Conversion of a 2-part MULTICS address into a main memory address
A Pentium selector
Conversion of a (selector, offset) pair to a linear address
Mapping of a linear address onto a physical address
Protection on the Pentium