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Experiment 2 Problem 1 Grain-128 stream cipherPowerPoint Presentation

Experiment 2 Problem 1 Grain-128 stream cipher

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Message / Ciphertext

m bits

Cryptographic

Key

Encrypt/Decrypt

k bits

1 bit

m bits

Ciphertext / Message

key of Alice and Bob - KAB

key of Alice and Bob - KAB

Network

Decryption

Encryption

Bob

Alice

Block vs. stream ciphers

M1, M2, …, Mn

m1, m2, …, mn

memory

Block

cipher

K

K

Stream

cipher

C1, C2, …, Cn

c1, c2, …, cn

Ci=fK(Mi)

ci = fK(mi, mi-1, …, m2, m1)

Every block of ciphertext

is a function of only one

corresponding blockof plaintext

Every block of ciphertext

is a function of the current and

all proceeding blocks of plaintext

Typical stream cipher

Sender

Receiver

Initialization

Vector - IV

Initialization

Vector - IV

Key - K

Key - K

Pseudorandom

Key

Generator

Pseudorandom

Key

Generator

keystream

ki

keystream

ki

mi

ci

ci

mi

plaintext

ciphertext

ciphertext

plaintext

ci = mi ki

message

mi

ki

ci

01110110101001010110101

11011101110110101110110

10101011011111111000011

keystream

ciphertext

mi = ci ki

ci

ki

mi

ciphertext

10101011011111111000011

11011101110110101110110

01110110101001010110101

keystream

message

Example of a simpler 5-stage LFSR

LFSR = Linear Feedback Shift Register

si

si+1

si+2

si+3

si+4

si+5

si+5 = si + si+1 + si+3

+ is used to denote XOR

si+7

si+96

si+38

si+70

si+81

. . . .

si

si+1

si+2

si+126

si+127

si+128

+ is used to denote XOR

Example of a simpler 5-stage NFSR

NFSR = Non-Linear Feedback Shift Register

bi

bi+1

bi+2

bi+3

bi+4

bi+5

bi+5 = bibi+1 + bi+3

+ is used to denote XOR

bmbn is used to denote bm AND bn

bi+26

bi+68 bi+84

. . . .

bi+56

bi+91

si

. . . .

bi

bi+1

bi+2

bi+126

bi+127

bi+128

+ is used to denote XOR

bmbn is used to denote bm AND bn

Output function in Grain-128

Key and IV Initialization

Phase 1

Initial state of NFSR:

bi = ki for i=0..127, where ki are bits of the key, k

Initial state of LFSR:

si = IVi for i=0..95, where IVi are bits of the

si = ‘1’ for i=96..127 initialization vector, IV

Phase 2

256 clock cycles of key mixing using connections

shown in the next slide

(output fed back and xor’ed with inputs to LFSR and NFSR)

Grain-128: Connections in the circuit

during Key & IV Initialization, Phase 2

Grain-128: Keystream Generation

Optimization for 2 bits per clock cycle

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