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Logic Synthesis 1985-2005. Death of Logic Synthesis. Rajeev Madhavan Magma Design Automation. The following discussion contains forward-looking statements, and our actual results may differ materially from those discussed here.

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Death of logic synthesis

Logic

Synthesis

1985-2005

Death of Logic Synthesis

Rajeev Madhavan

Magma Design Automation


The following discussion contains forward-looking statements, and our actual results may differ materially from those discussed here.

Additional information concerning factors that could cause such a difference can be found in Magma’s Annual Report on Form 10-K for the year ended March 31, 2003. Forward-looking statements speak only as of the earlier of the date first published or the date hereof. Magma disclaims any obligation to update forward-looking statements.

The Fastest Path from RTL to Silicon


Design starts by geometry trend during economic recession
Design Starts by Geometry: Trend during economic Recession statements, and our actual results may differ materially from those discussed here.

  • 0.18 micron is now mainstream technology.

  • Most leading-edge designs targeted for 0.13 micron.

  • Today 0.13 micron is fast becoming mainstream.

  • Leading design teams now preparing for 90nm.

Source: IBS ’03


Challenges of soc designs at 90nm and 65nm
Challenges of SoC Designs at 90nm and 65nm statements, and our actual results may differ materially from those discussed here.

  • 100M+ gate designs

    • 18mm X 18mm, 2000 I/Os, 500Mhz

    • Approximately 10M lines of RTL

  • 80+ engineers

    • Experts in synthesis, P&R, signal integrity, power analysis, design closure

  • $80M investment

    • Requires $160M in 2 years to realize break even

    • Where is the killer application for this??

Traditional design flows will make Moore’s law economically infeasible


Smaller geometries higher cost

$30M ~ $50M @ 90nm statements, and our actual results may differ materially from those discussed here.

Total Product Cost ($M)

50

Wireless chip case

40

Networking chip case

30

20

10

0.15

0.13um

90nm

0.18um

Source: IBS Inc.

Smaller Geometries= Higher Cost

Engineering Cost – 60% up

Product

Cost

Manufacturing Cost – 40% up

for each generation

NRE/Mask Cost – 100% up


We eda industry give you the pieces you assemble it
We (EDA industry) give you the pieces …. statements, and our actual results may differ materially from those discussed here. You assemble it …

Electronic Design

Assistance

Automation

ROI is essential to justify Silicon Usage

Reflects on State of the EDA industry


Synthesis history logic optimization infancy
Synthesis History - Logic Optimization -> Infancy statements, and our actual results may differ materially from those discussed here.

  • Logic Optimization

    • A lot of research in 1980’s

    • Birth of MIS/SIS and other optimizers

  • Companies were formed

    • RTL compilation followed

    • Mapper, buffering, sizing … lots of interesting work

  • Layout Engineers

    • APR had been automated

    • Fully done … boring … layout engineers


Synthesis middle age crisis
Synthesis – Middle age crisis statements, and our actual results may differ materially from those discussed here.

  • Around 1995

    • Capacity 10K gates, 3K cells per block

    • Manual time budgeting

    • Thousands of lines of scripts

    • Difficult to work with timing exceptions, latch based design

    • Wireload models


1990 s internet boom mantra time to market
1990’s Internet Boom Mantra - statements, and our actual results may differ materially from those discussed here.Time-to-Market

Time to 1 Million Units Sold

# Units

Sold

DVB

Cellular

VCR

Cable TV

PCS

PC

Color TV

B&W TV

DVD

1

Million

Units

5

10

15

20

Years

Source: D. Merriman, “Wireless Communications Report,” BIS, 1995 + Dataquest


1995 statements, and our actual results may differ materially from those discussed here.– .35m & 2M gates

2001 – .13m & 100M gates

Large, Complex Designs

PC – 7 years to 1M units

PlayStation – 3 days to 1M units

Rapid Time To Market

Reliability

Manufacturability

High-Quality Designs

90’s - Customer Requirements – The Boom Days

  • Unrelenting push for better size, speed, quality & cost.


Synthesis middle age break through
Synthesis – Middle age break through statements, and our actual results may differ materially from those discussed here.

  • In 1996, product introductions included:

    • Capacity stretched to 100K gates

    • Time budgeting introduced

    • Distributed processing added

    • Delay still based on random wireload models

  • More new companies formed

    • Ambit Design Systems


Ingredients for a successful startup
Ingredients For a Successful Startup statements, and our actual results may differ materially from those discussed here.

  • Right Technology

  • Right Place

  • Right Time


Startup 1 synthesis technology ambit
Startup #1 – Synthesis Technology - Ambit statements, and our actual results may differ materially from those discussed here.

  • Founded: 1994

  • Funding: $150K seed commitment - $135K.

  • Product: Logic Synthesis - V1.0 November 1996.


Ambit business proposition

Logical statements, and our actual results may differ materially from those discussed here.

Logical

Physical

(layout)

Timing (netlist)

Ambit – Business Proposition

  • Logic design was slow as tools was very slow and had limited capacity

  • Chip sizes were much bigger than logic design tools


Ambit tracing the dark alleys

1997 statements, and our actual results may differ materially from those discussed here.

1997/98

Excess financing

Problem

$4M … SGI, SUN, Chromatic

Benchmark showing great results after logic design- but bad layout results!

1996

Imminent Shutdown

Bridge loans

(mortgages)

Cadence/LSI

1995

Impossible to raise funding – attempt side product DFT

~ $500K (30+investors)

1994

Founded with $135K

Ambit: Tracing the Dark Alleys!


Traditional flow

Logic Synthesis statements, and our actual results may differ materially from those discussed here.

frozen sizes

frozen netlist

PDEF

SDF

RC

Placer

frozen placement

Optimization

manual

hacking

Router

Extractor

Traditional Flow

  • No physical knowledge in synthesis

  • Synthesis netlist unimplementable

  • Partitioning and budgeting for synthesis only

  • Timing from synthesis unachievable in layout

The only answer: Iterate


Ambit acquired in 1998

1997 statements, and our actual results may differ materially from those discussed here.

1998

1997/98

Excess financing

Problem

$4M … SGI, SUN, Chromatic

Benchmark showing great netlist results, bad layout results!

1996

Acquired by Cadence

Imminent Shutdown

Bridge loans

(mortgages)

Cadence/LSI

1995

Impossible to raise funding – attempt side product DFT

~ $500K (30+investors)

1994

Founded with $135K

Ambit: Acquired in 1998!


Ingredients for a successful startup1
Ingredients For a Successful Startup statements, and our actual results may differ materially from those discussed here.

  • Right Technology

  • Right Place

  • Right Time


Synthesis history old age
Synthesis History – Old Age …. statements, and our actual results may differ materially from those discussed here.

  • Physical Synthesis Evolution

    • Logic Optimization and Placement combined

    • Some used wireload

    • Others used fixed timing

  • New Companies Formed

    • Fixed timing gave larger capacity


Design flow getting obsolete quickly

Tape-Out statements, and our actual results may differ materially from those discussed here.

Physical Design

Logic Design

Masks

(place & route)

(synthesis)

CONVENTIONAL PHYSICAL DESIGN SYSTEM FLOW

Design Flow Getting Obsolete Quickly

Timing Closure Iterations

  • Control the iterations from increasing

  • Wireload Based Physical synthesis – patch work for better wire delay estimation started

  • Cost and complexity increasing


Key benefits of fixedtiming closer integration

Tape out statements, and our actual results may differ materially from those discussed here.

Tape out

TimingClosure

Timing convergence iterations

EXISTING SYSTEMS

Masks

Logic Design

Physical Design

Key Benefits of FixedTiming – Closer Integration

Predictable Handoff

Fixed Timing

Masks

Wireload Synthesis

Physical Design

Tape out

TimingClosure

Wireload based flows

Masks

Wireload Synthesis

Physical Design

Design Cycle Time (months)


EDA reaped change to physical synthesis statements, and our actual results may differ materially from those discussed here.

Tape out

Silicon Design Team

Physical Synthesis

Masks

Physical Design

Logic Design

Block ESP TimingSign-off

Foundry

Netlist


On going success criteria
On going success criteria … statements, and our actual results may differ materially from those discussed here.

  • Lower cost of manufacturing

    • Better performance on timing, area, SI and power

  • Shorter turnaround time (TAT) by 50% to 90%

    • Predictability – early feedback on achievable performance

  • Lower design cost by 30% to 50%

    • More gates per engineer, fewer licenses, shorter TAT

      Stand alone logic synthesis plays insignificant role

      Any capacity can now be synthesized flat ….


Maximizing yield for a given process

Logic Synthesis statements, and our actual results may differ materially from those discussed here.

??

Physical Synthesis

Routing

Design Verification

Design Rules

Mask

RET (OPC)

Process

Yield

Issues

Maximizing Yield For a given process

  • DRs cannot capture all manufacturability issues

    • The number and complexity of DRs are exploding

  • OPC is by no means DFM

    • OPC is done after design is completed (post-layout)

    • Getting more difficult to correct post-layout

  • Little is done during design

    • Fixing yield disturbs timing, area, power ……

    • Anything during synthesis, placement, routing?

More Complexities during tail end


Statistical design vs worst case design

Yield loss statements, and our actual results may differ materially from those discussed here.

0

slack

Statistical Design vs. Worst Case Design

Deep Nanometer Mandates Design Paradigm Shift

“Put elephant diet” – The low carb way!

Changes at Routing Stage

Statistical

Design

Optimization


Design imperatives

Logic statements, and our actual results may differ materially from those discussed here.

Synthesis

Place &

Route

.25u+ 0.18u 0.13u 0.09u 65nm

1990s 1999 2001 2003 2005

Design Imperatives

  • Wire delay dominates cell delay

  • Wireload model based synthesis breaks down

  • Need logic synthesis integrated with placement

InterConnect Synthesis

Physical Synthesis

Integrated RTL-GDSII system

Signal Integrity / Crosstalk

Need integrated router

Severe crosstalk, OCV problems

50M+ gate designs

Hundreds of macros

Yield/manufacturability problems

On chip variations (OCV)

Need integrated clock synthesis


Fate of logic synthesis
Fate of Logic Synthesis statements, and our actual results may differ materially from those discussed here.

  • Almost all optimizations are migrating downstream

  • Decisions can only be made further down the chain

  • Other EDA pieces will follow

    • Signoff in the loop!

      Resistance is futile. You will be (have been) assimilated


Customer problem solution value proposition

GDSII statements, and our actual results may differ materially from those discussed here.

GDSII

RTL

RTL

SignoffSystem

Customer Wish

Customer Problem/Solution/Value Proposition

  • Customer Problem: Flows aren’t correct-by-construction, costing productivity

  • Historic EDA Problem: Ship tools for revenue – not productivity!!!

  • Value Proposition: Deliver a correct-by-construction flow, and provide engines for signoff - making signoff to a checklist activity”

ImplementationSystem

Implementation+ Signoff

“Signoffin theLoop”

Older Systems

New Approach


Death of logic synthesis1

1985-2005 statements, and our actual results may differ materially from those discussed here.

You will be

Remembered …

…….

……….

……………

Death of Logic Synthesis


Contributions from logic synthesis technology
Contributions from Logic Synthesis Technology statements, and our actual results may differ materially from those discussed here.

  • RTL Compilation

    • Language support for Verilog and VHDL

    • Pragmas, templates …

    • Poor quality of logic generated will result in poor results

  • Technology Mapping

  • Logic Structuring/re-structuring

  • Data Path Compiler

    • Standard operators

    • Good architectures assist in good QOR


Ic silicon platform alternatives
IC Silicon Platform Alternatives statements, and our actual results may differ materially from those discussed here.

  • Design platform solutions to all IC Silicon alternatives

    • Specifically SOC’s that combine different architectures

  • Business models based on extended IP sales need to evolve

Create

Unified EDA Flow

Fusion

Create-SA

Standard Cell

Structured ASIC - BE

Performance / Density

Turn-Around/Flexibility

Blast Architecture

Structured

ASIC

FPGA

FPGA

Design Cost / NRE


Silicon design cost reduction re thinking

$30M ~ $50M @ 90nm statements, and our actual results may differ materially from those discussed here.

Total Product Cost ($M)

50

Wireless chip case

40

Networking chip case

30

20

10

0.15

0.13um

90nm

0.18um

Source: IBS Inc.

Silicon Design Cost Reduction … Re-thinking ...

Engineering Cost – 60% up

Product

Cost

Manufacturing Cost – 40% up

for each generation

NRE/Mask Cost – 100% up


Integrated approach for high complexity designs

RTL statements, and our actual results may differ materially from those discussed here.

Frontend

RTL

Goals

TIMING, POWER, NOISE

PROTOTYPE

RTL Synthesis

Floorplan

DFT Analysis

Physical Synthesis

VLSI

COMPILER

Process, Library

Backend

Physical Synthesis

Clock Tree Synthesis

SI-Driven Routing

GDS II

GDSII

Si Compiler

Design Closure

Gates/Engineer

Integrated Approach for High-Complexity Designs

Automated Approach for High-Complexity Designs

Electronic Design Assistance

Electronic Design Automation


The tall thin vlsi engineer for 65nm

RTL statements, and our actual results may differ materially from those discussed here.

Goals

VLSI

COMPILER

Process, Library

GDS II

Si Compiler

Design Closure

The TALL THIN VLSI ENGINEER for 65nm

  • There is no front end engineer, no DFT engineer, no backend engineer, no extraction/analysis ….

  • Engineers built along design domains – for now

    • Digital, Analog and RF


Death of logic synthesis2

1985-2005 statements, and our actual results may differ materially from those discussed here.

You will be

Remembered …

RTL

Datapath

Tech Mapping

Support platforms

Optimization Algorithms

Death of Logic Synthesis


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