Dsps for future wireless base stations
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DSPs for Future Wireless Base-Stations. Sridhar Rajagopal and Joseph R. Cavallaro May 8, 2000. This work is supported by Texas Instruments, Nokia, Texas Advanced Technology Program and NSF. Outline. Background DSP Implementation and Task Partitioning Reduced Complexity Algorithms

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DSPs for Future Wireless Base-Stations

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Dsps for future wireless base stations

DSPs for Future Wireless Base-Stations

Sridhar Rajagopal and Joseph R. Cavallaro

May 8, 2000

This work is supported by Texas Instruments, Nokia, Texas Advanced Technology Program and NSF


Outline

Outline

  • Background

  • DSP Implementation and Task Partitioning

  • Reduced Complexity Algorithms

  • VLSI Architecture

  • Extensions for DSPs


Evolution of wireless communications

Evolution of Wireless Communications

First Generation

Voice

Second/Current Generation

Voice + Low-rate Data (9.6Kbps)

Third Generation +

Voice + High-rate Data (2 Mbps) + Multimedia

W-CDMA


Communication system uplink

Noise +MAI

Base Station

Reflected Paths

Direct Path

User 1

User 2

Communication SystemUplink


Main processing blocks

Main Processing Blocks

Decoding

Channel Estimation

Detection

Baseband Layer of Base-Station Receiver


Current dsp implementation

C67 at 166MHz; Spreading Code = 31

Current DSP Implementation


Reasons for poor performance

Reasons for Poor Performance

  • Sophisticated, Compute-Intensive Algorithms

  • Need more MIPs/FLOPs performance

  • Unable to fully exploit pipelining or parallelism

  • Bit - level computations / Storage

  • Task Partitioning

    • Multiple DSPs, FPGAs


Iterative scheme for estimation

Iterative Scheme for Estimation

  • Tracking

  • Method of Gradient Descent

  • Stable convergence behavior

    • Symmetric, Positive Definite Rbb

    • Condition number - MAI, SNR, Preamble length

  • µ - reciprocal of maximum eigenvalue


Dsps for future wireless base stations

Comparison of Bit Error Rates (BER)

-1

10

-2

BER

10

O(K2N)

MF

ActMF

ML

ActML

O(K3+K2N)

-3

10

4

5

6

7

8

9

10

11

12

Signal to Noise Ratio (SNR)

Simulations - AWGN Channel

MF – Matched Filter ML- Maximum Likelihood ACT – using inversion


Dsps for future wireless base stations

0

10

MF - Static

MF - Tracking

ML - Static

ML - Tracking

-1

10

BER

-2

10

-3

10

4

5

6

7

8

9

10

11

12

SNR

Fading Channel with Tracking

Doppler = 10 Hz, 1000 Bits,15 users, 3 Paths


Vlsi implementation

VLSI Implementation

  • Channel Estimation as a Case Study

  • Area - Time Efficient Architecture

  • Real - Time Implementation

    • Minimum Area Overhead

  • Bit- Level Computations - FPGAs

  • Core Operations - DSPs


Area time tradeoffs

Area-Time Tradeoffs

  • Area-Constrained Architecture

    • Pico-cells ; lower data rates

  • Time-Constrained Architecture

    • Maximum achieve-able data rates

  • Area-Time Efficient Architecture

    • Real-Time with minimum area overhead


Dsps for future wireless base stations

Characteristics of Wireless Algorithms

  • Massive Parallelism

  • Bit-level Computations

  • Matrix Based Operations

    • Memory Intensive

  • Complex-valued Data

  • Approximate Computations


Instruction set extensions

Instruction Set Extensions

  • To accelerate Bit level computations in Wireless

  • Integer - Bit Multiplications

    • Multiuser Detection, Decoding, Cross Correlation

  • Bit - Bit Multiplications

    • Auto-Correlation, Channel Estimation

  • Useful in other Signal Processing applications

    • Speech, Video,,,


Simd parallelism

64-bit Register A

64-bit Register B

8

8

+

+

x

8

64-bit Register C

SIMD Parallelism


Integer bit multiplications

64-bit Register D[i][j]

8

8

+/-

+/-

8

8-bit Control

Register b[i]

64-bit Register D[i][j]

Integer - Bit Multiplications

64-bit Register C[j]

For i = 1..8, j= 1..8

D[i][j] = D[i][j] + b[i]*C[j] (Cross-Correlation)


Computational savings

Computational Savings

  • Avoid bit multiplications and control structures

  • 4 8-bit Multiply

    • Latency 3

  • 8 8-bit Add

    • Latency 1

  • Cross-Correlation Example

    • 64 multiply, 64 add


Conclusions

Conclusions

  • Architecture and Algorithms to meet real-time

  • Task Decomposition

    • Real Time with Multiple Processing Elements

  • Iterative Algorithms

    • Reduce Complexity, Simpler Implementation

  • VLSI Implementation

    • Real-Time with minimum Area Overhead

  • Extensions to DSPs for acceleration


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