Ee2420 digital logic summer ii 2013
Download
1 / 29

EE2420 – Digital Logic Summer II 2013 - PowerPoint PPT Presentation


  • 114 Views
  • Uploaded on

EE2420 – Digital Logic Summer II 2013. Set 12: Multiplexers, Decoders, Encoders, Shift Register Class book: Chapter 6 Online book: chapter 8. Hassan Salamy Ingram School of Engineering Texas State University. Multiplexer.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' EE2420 – Digital Logic Summer II 2013' - cuyler


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Ee2420 digital logic summer ii 2013
EE2420 – Digital LogicSummer II 2013

Set 12: Multiplexers, Decoders,

Encoders, Shift Register

Class book: Chapter 6

Online book: chapter 8

Hassan Salamy

Ingram School of Engineering

Texas State University


Multiplexer
Multiplexer

  • In its standard form, a multiplexer takes an N-bit control input to determine which of 2N data inputs will be passed to its single output.

  • In other words, a multiplexer selects one of multiple inputs

  • Functions may be implemented by using a combination of the control inputs and data inputs.


A 2 to 1 multiplexer
A 2-to-1 multiplexer

s

f

s

w

w

0

0

0

0

f

w

1

w

1

1

1

(b) Truth table

(a) Graphical symbol

w

0

s

f

w

1

(c) Sum-of-products circuit


A 4 to 1 multiplexer
A 4-to-1 multiplexer.

s

0

s

s

s

f

1

1

0

w

w

00

0

0

0

0

w

01

w

1

0

1

f

1

w

10

w

2

1

0

2

w

11

3

w

1

1

3

(a) Graphic symbol

(b) Truth table

s

0

w

0

s

1

w

1

(c) Circuit

f

w

2

w

3


Using 2 to 1 multiplexers to build a 4 to 1 multiplexer
Using 2-to-1 multiplexers to build a 4-to-1 multiplexer

s

1

s

0

w

0

0

w

1

1

0

f

1

w

0

2

w

1

3


A 16 to 1 multiplexer
A 16-to-1 multiplexer.

s

0

s

1

w

0

w

3

s

w

2

4

s

3

w

7

f

w

8

w

11

w

12

w

15


A practical application of multiplexers
A practical application of multiplexers

s

x

y

1

1

x

y

2

2

(a) A 2x2 crossbar switch

x

0

1

y

1

1

s

x

0

2

y

2

1

(b) Implementation using multiplexers


Synthesis of a logic function using multiplexers
Synthesis of a logic function using multiplexers

w

w

w

f

2

1

2

w

1

0

0

0

0

1

f

0

1

1

1

1

0

1

0

0

1

1

(a) Implementation using a 4-to-1 multiplexer

w

w

f

1

2

f

w

1

w

1

0

0

0

w

0

2

1

0

1

w

w

1

2

2

1

1

0

f

0

1

1

(c) Circuit

(b) Modified truth table


Implementation of the three input majority function using a 4 to 1 multiplexer
Implementation of the three-input majority function using a 4-to-1 multiplexer.

w

w

w

f

1

2

3

w

w

f

1

2

0

0

0

0

0

0

0

0

0

1

0

w

0

1

3

0

1

0

0

w

1

0

3

0

1

1

1

1

1

1

1

0

0

0

1

0

1

1

1

1

0

1

1

1

1

1

(a) Modified truth table

w

2

w

1

0

w

(b) Circuit

3

f

1


Three input xor implemented wit 2 to 1 multiplexers
Three-input XOR implemented wit 2-to-1 multiplexers 4-to-1 multiplexer.

w

w

w

f

1

2

3

0

0

0

0

0

0

1

1

w

Å

w

w

2

2

3

w

0

1

0

1

1

w

0

1

1

0

3

1

0

0

1

f

1

0

1

0

Å

w

w

2

3

1

1

0

0

1

1

1

1

(a) Truth table

(b) Circuit


Three input xor function implemented with a 4 to 1 multiplexer
Three-input XOR function implemented with a 4-to-1 multiplexer

w

w

w

f

1

2

3

0

0

0

0

w

3

w

0

0

1

1

2

w

1

0

1

0

1

w

3

w

0

1

1

0

3

1

0

0

1

f

w

3

1

0

1

0

1

1

0

0

w

3

1

1

1

1

(b) Circuit

(a) Truth table


The three input majority function implemented using a 2 to 1 multiplexer
The three-input majority function implemented using a 2-to-1 multiplexer.

w

w

w

f

1

2

3

f

0

0

0

0

w

1

0

0

1

0

w

w

0

2

3

0

1

0

0

w

+

w

1

2

3

0

1

1

1

1

0

0

0

1

0

1

1

1

1

0

1

1

1

1

1

(b) Truth table

w

1

w

2

w

3

f

(b) Circuit


What is a demultiplexer demux
What is a Demultiplexer (DEMUX)? multiplexer.

Demultiplexer

Block Diagram

1

2N

Input

(source)

Outputs

(destinations)

N

Select

Lines

DEMUX

  • A DEMUX is a digital switch with a single input (source) and a multiple outputs (destinations).

  • The select lines determine which output the input is connected to.

  • DEMUX Types

     1-to-2 (1 select line)

     1-to-4 (2 select lines)

     1-to-8 (3 select lines)

     1-to-16 (4 select lines)


Typical application of a demux
Typical Application of a DEMUX multiplexer.

Multiple Destinations

Single Source

Selector

B/W Laser

Printer

Fax

Machine

Color Inkjet

Printer

D0

D1

D2

D3

Pen

Plotter

X

DEMUX


Decoder
Decoder multiplexer.

  • In its standard form, a decoder takes an N-bit input and outputs 2N functions, each of which is active for exactly one input combination.

  • In other words, a decoder outputs the minterms of the inputs (or with inverted outputs, the maxterms)

  • Functions may be implemented with the addition of a single extra gate. For example, an OR gate may be used to combine minterms for a sum-of-products implementation or an AND gate may be used to combine maxterms for a product-of-sums implementation.


An n to 2 n binary decoder
An multiplexer.n-to-2n binary decoder.

w

y

0

0

n

n

2

inputs

w

outputs

n

1

y

n

Enable

2

1

En


w multiplexer.

w

y

y

y

y

En

1

0

0

1

2

3

w

y

0

0

0

0

0

1

0

0

1

w

y

1

1

0

1

0

1

0

0

1

y

2

1

1

0

0

0

1

0

y

En

3

1

1

1

0

0

0

1

x

x

0

0

0

0

0

(a) Truth table

(b) Graphical symbol

w

0

y

0

w

1

y

1

y

2

y

3

En

(c) Logic circuit

A 2-to-4 decoder.


A 3 to 8 decoder using two 2 to 4 decoders
A 3-to-8 decoder using two 2-to-4 decoders. multiplexer.

w

y

w

y

0

0

0

0

w

y

w

y

1

1

1

1

y

y

2

2

w

y

2

y

En

3

3

y

w

y

En

4

0

0

y

w

y

5

1

1

y

y

6

2

y

y

En

7

3


w multiplexer.

y

w

y

0

0

0

0

w

y

w

y

1

1

1

1

y

y

2

2

y

y

En

3

3

y

w

y

4

0

0

w

y

y

5

1

1

y

y

2

6

w

w

y

y

y

2

En

0

0

3

7

w

w

y

3

1

1

y

2

y

w

y

y

En

En

8

0

0

3

y

w

y

9

1

1

y

y

2

10

y

y

En

3

11

y

w

y

12

0

0

y

w

y

13

1

1

y

y

2

14

y

y

En

3

15

A 4-to-16 decoder built using a decoder tree.


A 4 to 1 multiplexer built using a decoder
A 4-to-1 multiplexer built using a decoder. multiplexer.

w

0

w

1

s

w

y

0

0

0

s

w

y

f

1

1

1

y

w

2

2

y

En

1

3

w

3


Decoders designing logic circuits
Decoders: Designing Logic Circuits multiplexer.

F = Sm(0,2)


A 2 m x n read only memory rom block
A 2 multiplexer.m x n read-only memory (ROM) block.

Sel

0

0/1

0/1

0/1

Sel

1

0/1

0/1

0/1

Sel

a

2

0

0/1

0/1

0/1

decoder

a

1

Address

m

-to-2

a

m

1

m

Sel

m

2

1

0/1

0/1

0/1

Read

d

d

d

Data

n

1

n

2

0


A 2 n to n binary encoder
A 2 multiplexer.n-to-n binary encoder.

w

0

y

0

n

n

2

outputs

inputs

y

n

1

w

n

2

1


A 4 to 2 binary encoder
A 4-to-2 binary encoder. multiplexer.

w

w

w

w

y

y

3

2

1

0

1

0

0

0

0

1

0

0

0

0

1

0

0

1

0

1

0

0

1

0

1

0

0

1

1

0

(a) Truth table

w

0

w

1

y

0

w

2

y

1

w

3


4 bit data shifter
4-bit Data Shifter multiplexer.

  • Data Shifter

    • A combinational logic shifter is a device that produces an output obtained by shifting its input

    • Right Shift: The Most Significant bit is called the fill bit and the Least Significant bit is called the spill bit

    • Left Shift: MSB is the spill bit – LSB is the fill bit

  • Processes:

    • Logical Shift => a logic zero is inserted in the fill position

    • Arithmetic => the sign bit is extended in a right shift

    • End-around [or rotate]


4 bit logical shifter problem statement
4-bit Logical Shifter multiplexer.Problem Statement

  • Step 1: Clear Problem Statement

    • Design and implement a 4-bit logical shifter that has 4-bit input “A”, 4-bit output “S”, and 1-bit controls X and Y where:


4 bit logical shifter conceptualization
4-bit Logical Shifter multiplexer.Conceptualization

  • Step 2: Conceptualization

    • This 4-bit shifter can be represented by the black-box model below with the associated Output Table


4 bit logical shifter solution simplification
4-bit Logical Shifter multiplexer.Solution/Simplification

  • Step 3: Solution/Simplification

    • The output table, with it’s different terms and exact duplication of bit values - - Should suggest a multiplexer

    • The logic functions describing the assignment of the values is:


4 bit logical shifter realization and verification
4-bit Logical Shifter multiplexer.Realization and Verification

  • Step 4: Realization

    • Those 4 output values can be implemented using four 4-to-1 mux’s as follows:

  • Step 5: Verification

    • Lab time! - - Does it really do what you designed it to do?

    • Return to that K-map/Truth table and be sure!


ad