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Basic Modeling Constructs

Basic Modeling Constructs. Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University. Entity Declaration. EBNF: see page 108

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Basic Modeling Constructs

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  1. Basic Modeling Constructs Instructors: Fu-Chiung Cheng (鄭福炯) Associate Professor Computer Science & Engineering Tatung University

  2. Entity Declaration • EBNF: see page 108 • Example:entity adder is port ( a : in word; b : in word; sum : out word );end entity adder; entity adder is port ( a, b : in word; sum : out word );end entity adder;

  3. Entity Declaration • Default values entity and_or_inv is port ( a1, a2, b1, b2 : in bit := '1'; y : out bit ); end entity and_or_inv; • If the port is used, the default values are ignored

  4. library ieee; use ieee.std_logic_1164.all; entity program_ROM is port ( address : in std_ulogic_vector(14 downto 0); data : out std_ulogic_vector(7 downto 0); enable : in std_ulogic ); subtype instruction_byte is bit_vector(7 downto 0); type program_array is array (0 to 2**14 - 1) of instruction_byte; constant program : program_array := ( X"32", X"3F", X"03", -- LDA $3F03 X"71", X"23", -- BLT $23 -- not in book others => X"00" -- end not in book -- . . . ); end entity program_ROM;

  5. Architecture Bodies • Architecture bodies describe the internal operations of modules • EBNF: see 110 • Example: architecture abstract of adder isbegin add_a_b : process (a, b) is begin sum <= a + b; end process add_a_b;end architecture abstract;

  6. Concurrent Statements • Process statements • Signal Assignments • Assert statements • Wait statemnets • Statements are executed when events occur

  7. Signal Declarations • EBNF: see page 111 • Example: next page

  8. architecture primitive of and_or_inv is signal and_a, and_b : bit; signal or_a_b : bit; begin and_gate_a : process (a1, a2) is begin and_a <= a1 and a2; end process and_gate_a; and_gate_b : process (b1, b2) is begin and_b <= b1 and b2; end process and_gate_b; or_gate : process (and_a, and_b) is begin or_a_b <= and_a or and_b; end process or_gate; inv : process (or_a_b) is begin y <= not or_a_b; end process inv; end architecture primitive;

  9. Signal Assignment • EBNF: see page 113 • Example:signal y : bit := '0';signal or_a_b : bit := '0';signal clk : bit := '0';process isbegin y <= not or_a_b after 5 ns; wait on or_a_b;end process ;

  10. Signal Assignment • Clock generator: clock_gen : process (clk) is begin if clk = '0' then clk <= '1' after T_pw, '0' after 2*T_pw; end if; end process clock_gen;

  11. Signal Assignment • Two-input multiplexer mux : process (a, b, sel) is begin case sel is when '0' => z <= a after prop_delay; when '1' => z <= b after prop_delay; end case; end process mux;

  12. Signal Attributes • Given a signal S and a value T of type time • S’delayed(T): delay by time T • S’stable(T): true if there has been no event on S in the time interval T up to the current time • S’quite(T): true if there has been no transaction on S in the time interval T up to the current time(T is optional, if T is omit, value 0 is assume) • S’transaction: a transition (of bit) when there is a transaction on S

  13. Signal Attributes • Given a signal S and a value T of type time • S’event: true if there is an event on S in the current simulation cycle • S’active: true if there is a transaction on S in the current simulation cycle • S’last_event: the time interval since the last event on S • S’last_active: the time interval since the last transaction on S • S’last_value: the value of S just before the last event on S

  14. Signal Attributes • Example: check setup time requirement if clk'event and (clk = '1' or clk = 'H') and (clk'last_value = '0' or clk'last_value = 'L') then assert d'last_event >= Tsu report "Timing error: d changed within setup time of clk"; end if;

  15. entity edge_triggered_Dff is port ( D : in bit; clk : in bit; clr : in bit; Q : out bit ); end entity edge_triggered_Dff; -------------------------------------------------- architecture behavioral of edge_triggered_Dff is begin state_change : process (clk, clr) is begin if clr = '1' then Q <= '0' after 2 ns; elsif clk'event and clk = '1' then Q <= D after 2 ns; end if; end process state_change; end architecture behavioral;

  16. Wait Statements • EBNF: see page 118 • Wait statement causes the process to suspend execution • Sensitivity clause: on signal_names • Condition clause: until boolean_expression • Timeout clause: for time_expression

  17. Wait Statements • Example: half_add : process is begin sum <= a xor b after T_pd; carry <= a and b after T_pd; wait on a, b; end process half_add

  18. Wait Statements • Example: half_add : process (a, b) is begin sum <= a xor b after T_pd; carry <= a and b after T_pd; end process half_add;

  19. entity mux2 is port ( a, b, sel : in bit; z : out bit ); end entity mux2; -------------------------------------------------- architecture behavioral of mux2 is constant prop_delay : time := 2 ns; begin slick_mux : process is begin case sel is when '0' => z <= a after prop_delay; wait on sel, a; when '1' => z <= b after prop_delay; wait on sel, b; end case; end process slick_mux; end architecture behavioral;

  20. Wait Statements • Example wait until clk = ‘1’; Cause the executing process to suspend until the value of the signal clk changes to ‘1’ • Note that if the wait statement does not include a sensitivity clause, the condition is tested whenever an event occurs on any of the signals mentioned in the condition • wait on clk until reset=‘0’; reset is tested when clk change

  21. Wait Statements • Clock generator: clock_gen : process is begin clk <= '1' after T_pw, '0' after 2*T_pw; wait until clk = '0'; end process clock_gen;

  22. Wait Statements • Example of timeout clausewait until trigger = '1' for 1 ms;cause the the executing process to suspend 1. until trigger change to 1 or 2. until 1 ms of simulation time has elapsed

  23. Wait Statements • Clock generator: clock_gen : process is begin clk <= '1' after T_pw, '0' after 2*T_pw; wait for 2*T_pw; end process clock_gen;

  24. Wait Statements • Test vector generation: generate all four possible combinations of values on signals test0 and test1 test_gen : process is begin test0 <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns; test1 <= '0' after 10 ns, '1' after 30 ns; wait; end process test_gen;

  25. Events and Transactions • Event: a signal value is changed by some waveforms. • Transaction: (time, value) pair is put on the driver • A transaction that expires generates a current driving value

  26. Events and Transactions

  27. Demo • Example ARCHITECTURE demo OF example IS SIGNAL a, b, c : BIT := '0'; BEGIN a <= '1' AFTER 15 NS; b <= NOT a AFTER 5 NS; c <= a AFTER 10 NS; END demo;

  28. 0 1

  29. Delta Delay • A delay of 0 in a signal assignment is called delta delay. • What happen if in a process we haves <= ‘1’; -- what happen if s:=‘1’; …if s=‘1’ then …

  30. Delta Delay Ex1 ENTITY timing IS PORT (a, b : IN BIT; z, zbar : BUFFER BIT); END ENTITY; -- ARCHITECTURE delta of timing IS BEGIN z_bar <= NOT z; // delta delay between z_bar and z z <= a AND b AFTER 10 NS; END delta;

  31. Delta Delay Ex2 ARCHITECTURE not_properly_timed OF figure_5_example IS SIGNAL w, x, y : BIT := '0'; BEGIN y <= c AND w; w <= NOT a; x <= a AND b; z <= x OR y AFTER 36 NS; END not_properly_timed;

  32. Assume at time zero signal a is assigned 0

  33. Delta Delay Ex3: ARCHITECTURE concurrent OF timing_demo IS SIGNAL a, b, c : BIT := '0'; BEGIN a <= '1'; b <= NOT a; c <= NOT b; END concurrent;

  34. Delta Delay Ex4: inverter chain ARCHITECTURE forever OF oscillating IS SIGNAL x: BIT := ‘0’; SIGNAL y: BIT := ‘1’; BEGIN x <= y; y <= NOT x; END forever;

  35. Architecture abstract of computer_system is subtype word is bit_vector(31 downto 0); signal address : natural; signal read_data, write_data : word; signal mem_read, mem_write : bit := '0'; signal mem_ready : bit := '0'; begin cpu : process is … begin … end process cpu; memory : process is … begin … end process memory; end architecture abstract; Figure 5.9

  36. cpu : process is variable instr_reg : word; variable PC : natural; -- . . . -- other declarations begin loop address <= PC; mem_read <= '1'; wait until mem_ready = '1'; instr_reg := read_data; mem_read <= '0'; wait until mem_ready = '0'; PC := PC + 4; -- . . . -- execute the instruction end loop; end process cpu;

  37. memory : process is type memory_array is array (0 to 2**14 - 1) of word; variable store : memory_array := ( 0 => X"0000_0000", 1 => X"0000_0004", 2 => X"0000_0008", 3 => X"0000_000C", 4 => X"0000_0010", 5 => X"0000_0014", others => X"0000_0000" ); begin wait until mem_read = '1' or mem_write = '1'; if mem_read = '1' then read_data <= store( address / 4 ); mem_ready <= '1'; wait until mem_read = '0'; mem_ready <= '0'; else -- . . . -- perform write access end if; end process memory;

  38. Delta Delay • Check Fig 5-10 on page 124 • EBNF of Delay mechanism: see page 124

  39. Transport and Inertial Delays • Signal assignment can be inertial or transport delay • Inertial delay: signal values less than its some delay are ignore • RC Delay model • transport delay: faithful transport the signal values • VHDL delay model: • Assignment with inertial mechanism • Assignment with inertial with reject mechanism • Assignment with transport mechanism

  40. Transport and Inertial Delays • Assignment with inertial mechanism • target1 <= waveform AFTER 5 NS; • A pulse whose width is less than 5 ns is rejected • Delay time = 5ns • Assignment with inertial with reject mechanism • target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS; • A pulse whose width is less than 3 ns is rejected • Delay time = 5 ns • Assignment with transport mechanism • target3 <= TRANSPORT waveform AFTER 5 NS; • Delay time = 5 ns

  41. Transport and Inertial Delays • Example: transmission_line : process (line_in) is begin line_out <= transport line_in after 500 ps; end process transmission_line; • See Fig 5.11 on page 125

  42. Transport and Inertial Delays • Example: asym_delay : process (a) is constant Tpd_01 : time := 800 ps; constant Tpd_10 : time := 500 ps; begin if a = '1' then z <= transport a after Tpd_01; else -- a = '0' z <= transport a after Tpd_10; end if; end process asym_delay; -- See Fig 5.12 on page 126

  43. Transport and Inertial Delays • Example: inv : process (a) is begin y <= inertial not a after 3 ns; end process inv; • See Fig 5.14 on page 127 (top part only)

  44. Fig 5.16 entity and2 is port ( a, b : in std_ulogic; y : out std_ulogic ); end entity and2; architecture detailed_delay of and2 is signal result : std_ulogic; begin gate : process (a, b) is begin result <= a and b; end process gate; delay : process (result) is begin if result = '1' then y <= reject 400 ps inertial '1' after 1.5 ns; elsif result = '0' then y <= reject 300 ps inertial '0' after 1.2 ns; else y <= reject 300 ps inertial 'X' after 500 ps; end if; end process delay; end architecture detailed_delay;

  45. Concurrent Signal Assignments • EBNF: see page 131 • Conditional signal assignment • Selected signal assignment

  46. Conditional Signal Assignments • EBNF: see page 132 • Example: zmux : z <= d0 when sel1 = '0' and sel0 = '0' else d1 when sel1 = '0' and sel0 = '1' else d2 when sel1 = '1' and sel0 = '0' else d3 when sel1 = '1' and sel0 = '1'; -- d3; • Last condition is redundant

  47. Conditional Signal Assignments • Same as zmux : process is begin if sel1 = '0' and sel0 = '0' then z <= d0; elsif sel1 = '0' and sel0 = '1' then z <= d1; elsif sel1 = '1' and sel0 = '0' then z <= d2; elsif sel1 = '1' and sel0 = '1' then z <= d3; -- else z <= d3; end if; wait on d0, d1, d2, d3, sel0, sel1; end process zmux;

  48. Conditional Signal Assignments scheduler : request <= first_priority_request after scheduling_delay when priority_waiting and server_status = ready else first_normal_request after scheduling_delay when not priority_waiting and server_status = ready else unaffected when server_status = busy else reset_request after scheduling_delay;

  49. scheduler : process is begin if priority_waiting and server_status = ready then request <= first_priority_request after scheduling_delay; elsif not priority_waiting and server_status = ready then request <= first_normal_request after scheduling_delay; elsif server_status = busy then null; else request <= reset_request after scheduling_delay; end if; wait on first_priority_request, priority_waiting, server_status, first_normal_request, reset_request; end process scheduler;

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