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L0 LKr trigger

L0 LKr trigger. Pixel based trigger processor (2x8 or 4x4 calorimeter cells tiles) Low granularity readout independent from the full granularity readout Fast readout after L0 for software triggers Region of Interest for Lkr full granularity readout. L0 LKr Trigger: architecture.

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L0 LKr trigger

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  1. TDAQ WG - CERN L0 LKr trigger • Pixel based trigger processor (2x8 or 4x4 calorimeter cells tiles) • Low granularity readout independent from the full granularity readout • Fast readout after L0 for software triggers • Region of Interest for Lkr full granularity readout

  2. TDAQ WG - CERN L0 LKr Trigger: architecture 13248 channels for the readout  864 channels (2x8 pixel supercells) for the trigger! FE boards: pulse reconstr (time, position, energy)‏ Concentrator boards: merging, sorting • Three mezzanines: • LKr interface (to be designed in 2011 -> 2012) • Trigger & RO TX (custom link for the trigger + ethernet for the readout) – under test • Trigger RX (custom link for the trigger) – tested • Three 9U crates

  3. TDAQ WG - CERN NA62 RX mezzanine NA62 RXmezzanine

  4. TDAQ WG - CERN NA62 TX Mezzanine NA62 TXmezzanine

  5. TDAQ WG - CERN NA62 TX Mezzanine • Tests ongoing • Power, clock, JTAG OK • Working on serdes interface

  6. TDAQ WG - CERN Cables • Prototypes assembled in our lab • Amphenol Halogen free cables (full production) should arrive now

  7. TDAQ WG - CERN Quad Gigabit Ethernet production • EDA-00472-V5 PCB quad GBE 74 Euro (50 pcs) – 325 Euro (10 pcs) • Marvel quad Ethernet transceiver 29 Euro (70 pcs) • Intel 4-port gigabit Ethernet MAC 113 Euro (90 pcs) • Miscellaneous components: 50 Euro (estimated) • Assembly and test: 80 Euro (estimated) • Around 350 Euro per board (VAT exempted, delivery at CERN) • -> Start whole PCB production now! • We will send an email: please let us know how many QGBE you need • PCB production: Somacis PCB Industries – Halogen free, impedance check, test coupon • Assembly and test: Aurel (?) – Halogen free + non halogen free issues

  8. TDAQ WG - CERN Data compression • Data compression studies with Altera Nios II soft processor • Work ongoing with our APE colleagues in Rome • Use of FPGA embedded processors for high performance data compression TWEPP 2011 26-30 September 2011 Vienna, Austria

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