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L’upgrade del Silicon Vertex Trigger (SVT) di CDF

L’upgrade del Silicon Vertex Trigger (SVT) di CDF. IFAE 2006 Alberto Annovi Istituto Nazionale di Fisica Nucleare Laboratori Nazionali di Frascati. SVT. Outline. the Silicon Vertex Trigger (SVT) Motivations Working principles Performance Upgrade. Why and how?.

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L’upgrade del Silicon Vertex Trigger (SVT) di CDF

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  1. L’upgrade del Silicon Vertex Trigger (SVT) di CDF IFAE 2006 Alberto Annovi Istituto Nazionale di Fisica Nucleare Laboratori Nazionali di Frascati SVT Alberto Annovi- IFAE 2006

  2. Outline • the Silicon Vertex Trigger (SVT) • Motivations • Working principles • Performance • Upgrade Alberto Annovi- IFAE 2006

  3. Why and how? • Trigger on B hadronic decays • B physics studies, eg. CP violation in B decays, Bs mixing • new particle searches, eg. Higgs, Supersymmetry • A b-trigger is particularly important at hadron colliders • large B production cross section for B physics • high energy available to produce new particles decaying to b quarks • overwhelming QCD background O(103) • need to improve S/B at trigger level • Detect large impact parameter tracks from B decays using the fact that (B)1.5 ps Technical challenge! secondary vertex primary vertex ~ 1 mm Alberto Annovi- IFAE 2006

  4. SVT: Input & Output Inputs: • L1 tracks from XFT (, pT) • digitized pulse heights from SVX II Functionalities: • hit cluster finding • pattern recognition • track fitting Outputs: • reconstructed tracks(d, , pT) Alberto Annovi- IFAE 2006

  5. SVT Design Constraints Detector Raw Data 7.6 MHz Crossing rate • 30 kHz input rate • O(103) SVX strips/event • 2-D low-res COT tracks • Latency O(20) sec • No Dead Time • Resolution offline • SVT upgrade keep it fast @ high luminosity Level 1 Trigger Level 1 pipeline: 42 clock cycles • Level 1 • 7.6 MHz Synchromous Pipeline • 5.5 s Latency • 30 kHz accept rate SVX read out after L1 L1 Accept Level 2 buffer: 4 events SVT here Level 2 Trigger • Level 2 • Asynchromous 2 Stage Pipeline • 20 s Latency • 800 Hz accept rate L2 Accept DAQ buffers At L3 it is too late L3 Farm Mass Storage (100 Hz) Alberto Annovi- IFAE 2006

  6. Roads • Then fit tracks inside roads. • Thanks to 1st step it is much easier • offline quality Tracking in 2 steps • Find low resolution track candidates called “roads”. Solve most of the pattern recognition Super Bin (SB) Alberto Annovi- IFAE 2006

  7. The Event Pattern matching The Pattern Bank ... Alberto Annovi- IFAE 2006

  8. Bingo scorecard AM: Associative Memory • Dedicated device: maximum parallelism • Each pattern with private comparator • Track search during detector readout Alberto Annovi- IFAE 2006

  9. New AM chip • Parallel pattern recognition is performed by the Associative Memory an array of AMchips • Pattern recognition happens during detector readout! • Standard Cell UMC 0.18 mm 10x10 mm die - 5000 patterns (was 128) 6 input hit buses (4Gbit/s) tested up to 40 MHz, simulated up to 50 MHz • 3000 production chips on April 2005 good yield 70% Original AM chip Alberto Annovi- IFAE 2006

  10. 2nd step: Track Fitting • Track confined to a thin pattern: fitting becomes easy • Linear expansion in the hit positions xi: • Chi2 = Sumk ( (cik xi)^2 ) • d = d0+ai xi ; phi = phi0+ bi xi ; Pt = ... • Fit reduces to a few scalar products: fast evaluation • (DSP, FPGA …) • Constants from detector geometry • Calculate in advance • Correction of mechanical alignments via linear algorithm • fast and stable • A tough problem made easy ! Alberto Annovi- IFAE 2006

  11. Constraint surface Alberto Annovi- IFAE 2006

  12. SVT crates in CDF counting room Alberto Annovi- IFAE 2006

  13. Performance @ 10x1031 35mm  33mm resol  beam  s = 48mm 20 ms SVT Impact parameter 0 10 20 30 40 50 Latency (ms) 0.8 Efficiency -500 -250 0 250 500 (mm) Given a fiducial offline track with SVX hits in 4/4 layers used by SVT 0.00 0.05 0.10 0.15 Impact parameter (cm) Alberto Annovi- IFAE 2006

  14. y f x d d d phi Online beamline fit & correction Raw <d> = Ybeamcosf – Xbeamsinf Subtracted Alberto Annovi- IFAE 2006

  15. SVT Hadronic B decays with SVT The SVT advantage: 3 orders of magnitude @ 3 x 1031 cm-2 s-1 • L1: • Two XFT tracks • Pt > 2 GeV; Pt1 + Pt2 > 5.5 GeV •  < 135° • L2: • d0>100 m for both tracks • Validation of L1 cuts with >20° • Lxy > 200 m • d0(B)<140 m Two body decays Alberto Annovi- IFAE 2006

  16. Signal yield: ~2300 events S/B 6.5 (peak value) Hadron-hadron mass distribution Ks D0 Mhh (GeV) See tomorrow talks for up to date B--> h h’ (M. Morello) and Bs mixing (Salamanna) SVT for hadronic Bs decays --> sesitivity at high Dms Alberto Annovi- IFAE 2006

  17. SVT upgrade Deadtime a L2 processing time * L1 Accept rate • Speed up SVT execution • cope with high lumi • reduce dead-time --> increase LVL1 bandwidth --> physics output • extra features • forward muon/electron trigger (Silicon only tracking) • release SVT upper impact parameter cut beyond 1mm • (CDF note PUB/CDF7359 to be published as NIM) • How to do that? • more powerful Associative Memory (32k --> 512k patterns) • Improve pattern recognition resolution • Reduce number of roads to fit • Replace AMS, RW, HB, TF with Pulsar boards • Support 512k pattern/wedge • Higher clock frequency --> faster track fitting & I/O Alberto Annovi- IFAE 2006

  18. Pisa 1st Pulsar:Sequencer & Road Warrior Associative Memory 512k patterns 3nd Pulsar:Track Fitter 2nd Pulsar:Hit Buffer Tsukuba Chicago Fermilab Chicago Alberto Annovi- IFAE 2006

  19. 24 AM++ installation • 2 AM++ per 30 degrees • 512k patterns • pattern width 240mm • was600mm with 32kpatt. • Currently using 512k patterns for maximum speed. • Extend tracking applications: • release upper I.p. cut • Pt down to 1.5GeV Lumi = 100E30 cm-2s-1 Alberto Annovi- IFAE 2006

  20. Pulsar in SVT++ • Implement new boards with Pulsars: • Fast enough to handle the new amount of data • SVT interface built in • Developers can concentrate on firmware (= board functionalities) The Pulsar board is a programmable board: 3 powerful FPGAs embedded RAM all CDF connectors modular mezzanines S-link I/O RAM extension Pulsar @ CDF --> FPGAs @ board devel. RAM mezzanine 4Mx48bits Alberto Annovi- IFAE 2006

  21. RW: Remove ghosts The CDF’s Road Warrior • majority logic: 4/5 SVX hits + XFT track • better efficiency • problem: duplicate roads (ghost) • because of missing layers • a common problem • A clean solution for ghost removal: • the road warrior board receives roads as they are found • store them in a dedicated Associative Memory • FPGA based • each road is compared on-the-fly with previous roads • AM algorithm: identify and drop duplicate roads • O(10) clock cycles latency proceedings of 2004 IEEE (NSS / MIC), Rome, Italy, 16-22 Oct 2004 Alberto Annovi- IFAE 2006

  22. impact of L2 upgrades on L1 bandwidth • full SVT upgrade • lumi 150E30 Before SVT Upgrade Lumi 20-50E30 Dead time % Summer 2005 Lumi 90E30 Lumi 45E30 L1 accept rate (Hz) 18KHz 25KHz +7kHz (+40%) L1A bandwidth @ double inst. lumi. Alberto Annovi- IFAE 2006

  23. SVT What next ? Next challenge is silicon tracking at both Level 1 & Level 2 SLIM5 (LVL1) Fast Track (LVL2) LHC, Super B factory IEEE Trans.Nucl.Sci. 51:391-400,2004 Alberto Annovi- IFAE 2006

  24. SLIM5: Tracking (detector + TDAQ) R&D for SuperB but TDAQ could be OK for Level 1 at SLHC Main problem: AM input Bandwidth, even if powerful: >10 Gbits/sec  divide the detector in thin f sectors. Each AM searches in a small Df 1 AM for each enough-small Df space-time Patterns Hits: position+time stamp All patterns inside a single chip N chips for N overlapping events identified by the time stamp AMchip receives up to 6 parallel buses for 6 layers at frequency: AMchip now: 50 MHz (Level 2) Next generation: 100 MHz or more Goal: use SAME CHIP for Level 2 & 1 Event1 AMchip1 Event2 AMchip2 Event3 AMchip3 EventN AMchipN Alberto Annovi- IFAE 2006

  25. The design and construction of SVT was a significant step forward in the technology of fast track finding We use a massively parallel/pipelined architecture combined with some innovative techniques such as the associative memory, linearized track fitting and road warrior CDF is triggering on impact parameter and collecting data leading to significant physics results B-physics, and not only, at hadron colliders substantially benefits of on-line tracking with off-line quality The system is modular and easy to upgrade The SVT technology is ready for other applications! SUMMARY Alberto Annovi- IFAE 2006

  26. BACKUP SLIDES Alberto Annovi- IFAE 2006

  27. 10.6 cm 2.5 cm 90 cm SVX II f-sector Alberto Annovi- IFAE 2006

  28. AB<6:0>( R/W MODE) SELP<2:0> ADDRESS DECODER SELECT PLANE DECODER pattern 0 pattern 1 pattern 127 layer0 12 bits word 12 bits compar. HIT BIT HIT BIT HIT BIT 12 bits word 12 bits compar. 12 bits word 12 bits compar. layer1 layer2 DATA BUS MULTIPLEXER layer3 layer4 layer5 COUNT HIT COUNTER OPC<3:0> SHIFT ENP* CONTROL MATCH BIT SEL* CLKB ADDRESS ENCODER CLKA AB<6:0>(OUTPUT MODE) OR* AM chip internal structure DB<11:0> Alberto Annovi- IFAE 2006

  29. Hit Finders raw data from SVX front end Sequencer Associative Memory COT tracks fromXTRP x 12 phi sectors roads RoadWarrior 12 fibers hits Track Fitter to Level 2 Merger hits Hit Buffer RW: Remove ghosts Upgrading SVT • Reduce SVT processing time: c1+c2*N(Hit) +c3*N(Comb.) • More patterns thinner roads  less fakes • Move Road Warrior before the HB • New TF++, HB++, AMS++, AM++ @ > 40MHz Alberto Annovi- IFAE 2006

  30. D xi From non-linear to linear constraints Non-linear geometrical constraint for a circle: F(x1 , x2 , x3 , …) = 0 But for sufficiently small displacements: F(x1 , x2 , x3 , …) ~ a0 +a1Dx1 + a2Dx2 + a3Dx3 + … = 0 with constant ai (first order expansion of F) Alberto Annovi- IFAE 2006

  31. Dead Time vs. L1 Accept Rate SVT @ 3 x 1032 SVT @ 0.5 x 1032 UPGRADE @ 3 x 1032 Alberto Annovi- IFAE 2006

  32. Silicon only no XFT SVXonly impact parameter distribution • Good tracks from just 4 closely spaced silicon layers • I.p. as expected due to the lack of curvature information s ~ 87 mm Alberto Annovi- IFAE 2006

  33. The Device AM Sequencer SuperStrip AM Board Hit Finder Hits Detector Data Matching Patterns Roads Roads + Corresponding Hits Hit Buffer L2 CPU Tracks + Corresponding Hits Track Fitter Alberto Annovi- IFAE 2006

  34. Where could we insert FTK? 2nd output 1st output CALO MUON TRACKER Very low impact on DAQ PIPELINE LVL1 Ev/sec = 50~100 kHz ROD FE FE Fast Track + few (Road Finder) CPUs high-quality tracks: Pt>1 GeV Buffer Memory Buffer Memory Raw data ROBs Track data ROB Fast network connection No change to LVL2 CPU FARM (LVL2 Algorithms) Alberto Annovi- IFAE 2006

  35. AMS/RW status (Pisa) • AMS and RW firmware implemented and tested • next step implement SVT firmware tools • ON SCHEDULE Pisa had the most risky responsibilities, but we are now in very good shape Alberto Annovi- IFAE 2006

  36. Non italian responsabilities • Pulsars • Pulsar production arrived • Large RAMmezzanine production done • Small RAMmezzanineprototype under test • ON SCHEDULE • TF • First firmware written • Standalone tests starting • ON SCHEDULE • HB • Firmware writing just started • BEHIND SCHEDULE • More man power (firmware engineer joined) Alberto Annovi- IFAE 2006

  37. SVT upgrade people • AM++ & AMSRW: A. Annovi, A. Bardi, M. Bitossi, M.Dell’Orso, P. Giannetti, P. Giovacchini, M. Piendibene, F. Spinella, L. Sartori, R. Tripiccione, S. Torre, I. Pedron, P. Catastini, S. Belforte, L. Ristori • HB++: I. Furic, T. Maruyama, S. Chappa, M. Aoki, E. Berry • TF++ & SRAM mezzanines: J. Adelman, U. Yang, F. Tang, M. Shochet, H. Sanders • Software: R. Carosi, S. Torre, B. Simoni, A. Annovi, P. Giovacchini, M. Rescigno, B. Di Ruzza, A. Cerri, J. Bellinger, G. Volpi, F. Sforza • Great support from Pulsar, DAQ, review committee,Silicon and operations people& Dervin’s group • INFN & Fermilab support Alberto Annovi- IFAE 2006

  38. TRIGGER: Tracking @ Level 2 & Level 1 • Atlas/CDF USA-Pisa group working for physics case for • FTK (Gruppo V –Pisa project 2000-02) @ Level 2 • http://hep.uchicago.edu/cdf/shochet/ftk_12_05/meeting.html • Proposal discussed during 2006 – • If approved  USA funds autumn 2006 • a) small prototype (using CDF AMchip) as soon as possible; • b) upgrade for high luminosity; • c) upgrade for SLHC • Italy will be required to partecipate • Try to use same AMchip for simplified tracking @ Level 1 Alberto Annovi- IFAE 2006

  39. Summer 2005 installation TF: RMS=18 TF++: RMS=10.7 Save ~10ms @ 100E30 Alberto Annovi- IFAE 2006

  40. New AM chip • Standard Cell UMC 0.18 mm 10x10 mm die - 5000 patterns 6 input hit buses tested up to 40 MHz, simulated up to 50 MHz • 116 prototype chips on September 2004 MPW run – low yield 37% • 3000 production chips on April 2005 good yield 70% private masks  better process parameter tuning for dense memory Alberto Annovi- IFAE 2006

  41. AM chip & system • Undoable with standard electronics (90’s) • Full custom VLSI chip - 0.7mm (INFN-Pisa) • 128 patterns, 6x12bit words each • Working up to 40 MHz • Limit to 2-D • 6 layers: 5 SVX + 1 COT • ~250 micron bins  32k roads / 300j sector • >95% coverage for Pt > 2 GeV Alberto Annovi- IFAE 2006

  42. Upgrade is on schedule AM++ Real data AMS/RW • AM++ and RW with 32k patterns have been already used in test runs for data taking • Plan to install AM++ with 32k pattern in July • Studies of 128k patterns coverage and efficiency are underway • Plan to install TF++ as soon as it will be ready (August) then move to 128k • HB++ expected to be installed during fall with 512k pattern memory Alberto Annovi- IFAE 2006

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