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Dec Hex Bin. 14 E 00001110. ORG ; FOURTEEN. Interrupts In x86 PC. OBJECTIVES this chapter enables the student to:. Explain how the x86 executes interrupts by using the interrupt vector table and interrupt routines. List the differences between interrupts and CALL instructions.

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Slide1 l.jpg

Dec Hex Bin

14 E 00001110

ORG ; FOURTEEN

Interrupts

In x86 PC


Objectives this chapter enables the student to l.jpg

OBJECTIVESthis chapter enables the student to:

  • Explain how the x86 executes interrupts by using the interrupt vector table and interrupt routines.

  • List the differences between interrupts andCALL instructions.

  • Describe the differences between hardwareand software interrupts.

  • Examine the ISR for any interrupt, given itsinterrupt number.

  • Describe the function of each pin of the 8259 programmable interrupt controller (PIC) chip.


Objectives this chapter enables the student to3 l.jpg

OBJECTIVESthis chapter enables the student to:

(cont)

  • Explain the purpose of each of the four control words of the 8259 and demonstrate how theyare programmed.

  • Examine the interrupts in x86 PCs.


14 1 8088 86 interrupts l.jpg

14.1: 8088/86 INTERRUPTS

  • An interrupt is an external event that informs the CPU that a device needs its service.

    • In 8088/86 there are a total of 256 interrupts.

      • INT 00, INT 01, ..., INT FF (sometimes called TYPEs).

  • When an interrupt is executed the processor:

    • Saves the flag register (FR), instruction pointer (IP),and code segment register (CS) on the stack,.

    • Goes to a fixed memory location.

      • In x86, always four times the value of the interrupt number.


14 1 8088 86 interrupts interrupt service routine isr l.jpg

14.1: 8088/86 INTERRUPTSinterrupt service routine (ISR)

When an interrupt is invoked it is asked to run a program to performa certain service.

There must be a program associated with every interrupt .

This program is commonly referred to as an interrupt service routine (ISR), and also called the interrupt handler.

When an interrupt is invoked, the CPU runs the interrupt service routine.


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14.1: 8088/86 INTERRUPTS interrupt service routine (ISR)

  • For every interrupt thereare allocated four bytesof memory in the interrupt vector table.

  • Two bytes for the IP.

  • Two for the CS of the ISR.

    • These locations provide the addresses of the interruptservice routine for which the interrupt was invoked.

  • The lowest 1024 bytes of memory space are set aside for the interrupt vector table.


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14.1: 8088/86 INTERRUPTS interrupt service routine (ISR)


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14.1: 8088/86 INTERRUPTS differences between INT and CALL

  • What is the difference between…

    • INT instruction - which saves the CS:IP of the following instruction and jumps indirectly to the subroutine associated with the interrupt.

    • A CALL FAR instruction, which also saves CS:IPand jumps to the desired subroutine (procedure)?


14 1 8088 86 interrupts differences between int and call9 l.jpg

14.1: 8088/86 INTERRUPTS differences between INT and CALL

  • A "CALL FAR " instruction…

    • can jump to any location within the 1-megabyte address range of the 8088/86 CPU.

      • The "INT nn" goes to a fixed memory location in the interrupt vector table to get the address of the interrupt service routine.

    • is used in the program instructions, but an externally activated hardware interrupt can come in any time, requesting CPU attention.

    • cannot be masked (disabled), but "INT nn" belonging to externally activated hardware interrupts can be masked.

    • auto-saves only CS:IP of the next instruction on the stack.

      • "INT nn" saves FR (flag register) also.


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14.1: 8088/86 INTERRUPTS differences between INT and CALL

  • "INT nn" is a 2-byte instruction where the first byte is for the opcode & the second the interrupt number.

    • A maximum of 256 (INT 00 INT FFH) interrupts.

      • Some are used for software interrupts; some for hardware.


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14.1: 8088/86 INTERRUPTS categories of interrupts

  • Three x86 pins are associated with hardware interrupts...

    • INTR (interrupt request)

    • NMI (nonmaskable interrupt)

    • INTA (interrupt acknowledge)

  • INTR is a CPU input signal, which can be masked (ignored) & unmasked through use CLI and STI.

  • NMI, also an input signal into the CPU, cannot be masked and unmasked using CLI & STI.

    • For this reason, it is called a nonmaskable interrupt.


14 1 8088 86 interrupts hardware interrupts l.jpg

14.1: 8088/86 INTERRUPTS hardware interrupts

  • INTR and NMI are activated externally by putting5V on the x86 microprocessor NMI & INTR pins.

    • On activation of either interrupt, x86:

      • Finishes the instruction it is executing.

      • Pushes FR & CS:IP of the next instruction onto the stack.

      • Jumps to a fixed location in the interrupt vector table and fetches the CS:IP for the interrupt service routine (ISR) associated with that interrupt.

  • At the end of the ISR, IRET causes the CPU to get (pop) back its original FR and CS:IP from the stack.

    • Forcing the CPU to continue at the instructionwhere it left off when the interrupt came in.


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14.1: 8088/86 INTERRUPTS hardware interrupts

  • Intel has embedded "INT 02" in x86, only for NMI.

    • Whenthe NMI pin is activated, the CPU location 00008to get the address (CS:IP) of the ISR.

      • Memory locations 00008, 00009, 0000A, and 0000Bcontain the 4 bytes of CS:IP of the ISR belonging to NMI.

  • There is no specific location in the vector table assigned to INTR.

    • Allowed to use any "INT nn" not previously assigned.

    • The 8259 programmable interrupt controller (PIC) chip can be connected to INTR to expand the number of hardware interrupts to 64.


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14.1: 8088/86 INTERRUPTS software interrupts

  • An ISR called as a result of execution of an x86 instruction such as "INT nn“ is referred to as a software interrupt.

    • As it was invoked from software, not external hardware.

      • DOS "INT 21H" function calls,and video interrupts "INT 10H".

      • Can be invoked in code like a CALL or other x86 instruction

      • Some of the interrupts are associated with predefined functions.


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14.1: 8088/86 INTERRUPTS software interrupts

Interrupts INT 05 to INTFF can be used for either software or hardware interrupts.

INT 00 to INT 04 have predefined functions.

INT 00 (divide error)

INT 01 (single step)

INT 03 (breakpoint)

INT 04 (signed number overflow)

Figure 14-1 Intel's List of Designated Interrupts for the 8088/86


14 1 8088 86 interrupts interrupts and the flag register l.jpg

14.1: 8088/86 INTERRUPTS interrupts and the flag register

  • Two flag register bits are associated with interrupt:

    • D9, or IF (interrupt enable flag)

    • D8, or TF (trap or single step flag).

    • OF (overflow flag) can be used by the interrupt.


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14.1: 8088/86 INTERRUPTS processing interrupts

  • When 8088/86 processes any interrupt:

    • 1. The flag register (FR) is pushed onto the stack &SP is decremented by 2, as FR is a 2-byte register.

    • 2. The IF (interrupt enable flag) & TF (trap flag) areboth cleared. (IF = 0 and TF = 0).

    • 3. The current CS is pushed onto the stack andSP is decremented by 2.

    • 4. The current IP is pushed onto the stack and SPis decremented by 2.


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14.1: 8088/86 INTERRUPTS processing interrupts

  • When 8088/86 processes any interrupt:

  • 5. The INT number (type) is multiplied by 4 to get the physical address of the location within the vector tableto fetch the CS and IP of the interrupt service routine.

  • 6. From the new CS:IP, the CPU starts to fetch and execute instructions belonging to the ISR program.

  • 7. The last instruction of the interrupt service routine must be IRET, to get IP, CS, and FR back from the stack and make the CPU run the code where it left off.


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14.1: 8088/86 INTERRUPTS software interrupts

A conditional or exception interrupt.

Invoked by the processor when there are conditions (exceptions) the CPU is unable to handle.

INT 00 invokes by when there is an attempt to divide a number by zero.

INT 00 is also invoked if the quotientis too large to fit into the assigned register when executing a DIV.

INT 00 to INT 04 have predefined functions.

INT 00 (divide error)


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14.1: 8088/86 INTERRUPTS software interrupts

Intel designated INT 01 specificallyfor implementation of single-stepping instructions for program tracing.

The trap flag (TF), D8 of the flag register, must be set to 1.

After execution of each instruction, 8088/86 jumps to physical location 00004 to fetch CS:IP of the interrupt service routine.

INT 00 to INT 04 have predefined functions.

INT 01 (single step)


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14.1: 8088/86 INTERRUPTS hardware interrupts

All Intel x86 processors have a pin designated NMI, an active-high input, and has reserved INT 02 for NMI.

When the NMI pin is activated by a high (5V) signal, the CPU jumps to physical memory location 00008 to fetch the CS:IP of the ISR routine associated with NMI.

INT 00 to INT 04 have predefined functions.

INT 02 (nonmaskable interrupt)


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14.1: 8088/86 INTERRUPTS software interrupts

Intel has set aside INT 03 for the implementation of breakpoints in software engineering.

A breakpoint is used to examine CPU and memory after the execution of a group of instructions.

INT 3 is the fact is a 1-byte instruction.

INT 00 to INT 04 have predefined functions.

INT 03 (breakpoint)


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14.1: 8088/86 INTERRUPTS software interrupts

Invoked by signed number overflow,& associated with the INTO (interrupt on overflow) instruction.

If instruction INTO is placed after a signed number arithmetic or logic operation such as IMUL or ADD, the CPU will activate INT 04 if OF = 1.

If OF = 0, INTO is is bypassed, acting as a NOP (no operation) instruction.

INT 00 to INT 04 have predefined functions.

INT 04 (signed number overflow)


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14.2: x86 PC AND INTERRUPT ASSIGNMENT

  • Of 256 possible interrupts in the x86…

    • Some are used by the PC peripheral hardware. (BIOS)

    • Some are used by the Microsoft operating system.

    • The rest are available for programmers of software applications.


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14.2: x86 PC AND INTERRUPT ASSIGNMENT

See the entire interrupt list on page 375 of your textbook.


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14.2: x86 PC AND INTERRUPT ASSIGNMENT examining the interrupt vector table

Using DEBUG's dump command to examine the interrupt vector table of a x86 PC, regardless of CPU it contained.


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14.2: x86 PC AND INTERRUPT ASSIGNMENT examining the interrupt vector table

  • From the CS:IP address of the ISR, it is possibleto determine which source provides the service.

    • DOS or BIOS.


14 2 x86 pc and interrupt assignment a nalyzing an x86 interrupt service routine l.jpg

14.2: x86 PC AND INTERRUPT ASSIGNMENT analyzing an x86 interrupt service routine

  • The interrupt 12H service is available on any PC with an x86 microprocessor.

  • The job of INT 12H is to copy the value of the data area used by BIOS from memory locations 00413H and 00414H into AX and return.

    • A function of the BIOS POST is to test & count totalK bytes of installed conventional RAM, and write itin memory locations 00413H and 00414H

  • After INT 12H, AX will then contain the totalK bytes of conventional RAM memory.


14 2 x86 pc and interrupt assignment a nalyzing an x86 interrupt service routine29 l.jpg

14.2: x86 PC AND INTERRUPT ASSIGNMENT analyzing an x86 interrupt service routine

Interrupt Service Routine in theIBM PC Technical Reference:


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14.2: x86 PC AND INTERRUPT ASSIGNMENT INT 12H: checking the RAM size on the PC


14 2 x86 pc and interrupt assignment int 12h checking the ram size on the pc31 l.jpg

14.2: x86 PC AND INTERRUPT ASSIGNMENT INT 12H: checking the RAM size on the PC


14 3 8259 interrupt controller l.jpg

Figure 14-3 8259A Programmable Interrupt Controller

14.3: 8259 INTERRUPT CONTROLLER

  • x86 has only pins INTR& INTA for interrupts.


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14.3: 8259 INTERRUPT CONTROLLER

The Intel 8259 programmable interrupt controller (PIC) makes expansionof the number of hardware interrupts much easier.

Figure 14-4 Partial Block Diagram of the 8259A


14 3 8259 interrupt controller pins l.jpg

14.3: 8259 INTERRUPT CONTROLLERpins

  • CAS0, CAS1, and CAS2 - can be used to setup several 8259 chips to expand the numberof hardware interrupts to 64.

    • By cascading 8259 chips in a master/slave configuration.

      • To use 8259 in slave mode, the chip must be programmedand CAS0 to CAS2 are ignored.

  • SP/EN, slave programming/enable - in buffered mode, an output signal from 8259 to activate the transceiver (EN).

    • In nonbuffered mode, an input signal into the 8259.

      • SP = 1 for the master and SP = 0 for the slave.


14 3 8259 interrupt controller pins35 l.jpg

14.3: 8259 INTERRUPT CONTROLLERpins

  • INT - an output connected to INTR of the x86.

  • INTA - input to the 8259 from INTA of the x86.

  • IR0 to IR7, interrupt request - hardware interrupts.

    • When a HIGH is put on any interrupt from IR0 to IR7,8088/86 will jump to a vector location.

    • For each IR there exists a physical memory locationin the interrupt vector table.

      • The x86 has 256 hardware or software interrupts.(INT 00–INT FF)


14 3 8259 interrupt controller control words and ports l.jpg

Figure 14-3 8259A Programmable Interrupt Controller

14.3: 8259 INTERRUPT CONTROLLERcontrol words and ports

  • Four control wordsassociated with the 8259:

  • ICW1 (initialization command word); ICW2; ICW3; ICW4.

  • There is only one address line A0 to communicate with the chip.


14 3 8259 interrupt controller control words and ports37 l.jpg

14.3: 8259 INTERRUPT CONTROLLERcontrol words and ports

Table 14-3 and Example 14-7 show the values that A0 and CS must take to initialize the 8259.


14 3 8259 interrupt controller control words and ports38 l.jpg

14.3: 8259 INTERRUPT CONTROLLERcontrol words and ports

  • ICW1, initialization command word 1 - functions to make a distinction between ICW2, ICW3, and ICW4 when they are sent to the same address of 8259.

    • D0, LSB of ICW1, tells 8259 if it should look for ICW4or not.

    • If D1 is high, it knows the system is configured in slave mode should not expect any ICW3 in the initialization sequence.

      • Initialization must always start with ICW1, followed by ICW2, and finally the last one, if needed; there is no jumping ahead.


14 3 8259 interrupt controller control words and ports39 l.jpg

14.3: 8259 INTERRUPT CONTROLLERcontrol words and ports

  • ICW1, initialization command word 1.

D2 is always set low (= 0) for x86.

D3 chooses between level triggering or edge triggering of the input signals IR0–IR7.

D4 must always be high.

D5, D6, and D7 are all low for x86 processors.

Figure 14-5 ICW Formats (ICW1 and ICW2)for the 8259


14 3 8259 interrupt controller control words and ports40 l.jpg

14.3: 8259 INTERRUPT CONTROLLERcontrol words and ports

  • ICW2, initialization command word 2 - assigns interrupt numbers to IR0–IR7.

    • The 8-bit INT type number assigned to the corresponding IR0 through IR7 is formed by the lower three bits D3–D7. (T3 through T7)

      • Lower three bits, D0, D1, and D2, vary from 000 to 111.


14 3 8259 interrupt controller control words and ports41 l.jpg

14.3: 8259 INTERRUPT CONTROLLERcontrol words and ports

  • ICW2, initialization command word 2.

D3–D7 can only be programmed according to the assignment ofthe INT type.

The lower bits are provided by 8259, depending on which interrupt of IR0 to IR7is activated.

Figure 14-5 ICW Formats (ICW1 and ICW2)for the 8259


14 3 8259 interrupt controller control words and ports42 l.jpg

14.3: 8259 INTERRUPT CONTROLLERcontrol words and ports

  • ICW3, initialization command word 3 - used only when two or more 8259s are cascaded.

    • A single 8259 can be connected to eight slave 8259s.

      • In cascade mode, there are separate ICW3 wordsfor the master and the slave.

  • ICW4, initialization command word 4 - D0 indicates the processor mode. (PM)

    • D0 equals 1 for the 8088/86 and 0 for the 8080/8085.

    • D1 is AEOI (automatic end of interrupt), is high it eliminates the need for an EOI instruction to be present before the IRET (interrupt return) instruction in the interrupt service routine.


14 3 8259 interrupt controller control words and ports43 l.jpg

14.3: 8259 INTERRUPT CONTROLLERcontrol words and ports

The 8259 can work in either buffered or nonbuffered mode.

Figure 14-6a & b

ICW Formats (ICW3 and CW4)for the 8259 - Master & Slave


14 3 8259 interrupt controller control words and ports44 l.jpg

14.3: 8259 INTERRUPT CONTROLLERcontrol words and ports

SFNM, special fully nested mode must be used when8259 is in master mode,

Figure 14-6a & b

ICW Formats (ICW3 and CW4)for the 8259 - Master & Slave


14 3 8259 interrupt controller masking prioritization ir0 ir7 interrupts l.jpg

14.3: 8259 INTERRUPT CONTROLLERmasking/prioritization IR0–IR7 interrupts

What happens if more than one of interruptsIR0–IR7 is activated at the same time?

Can we mask any of the interrupts?

What about responding to another interruptwhile an interrupt is being serviced?


14 3 8259 interrupt controller operation command word ocw l.jpg

There are three operation command words:OCW1, OCW2, OCW3.

14.3: 8259 INTERRUPT CONTROLLERoperation command word OCW

  • After ICW1, ICW2, and ICW4 have been issued to initialize the 8259, 8088/86 is ready to receive hardware interrupts through 8259's IR0–IR7 pins.

    • After the process of initialization, the operation command word, OCW, can be sent to mask any of IR0–IR7, or change the priority assigned to each IR.


14 3 8259 interrupt controller operation command word ocw47 l.jpg

14.3: 8259 INTERRUPT CONTROLLERoperation command word OCW

  • With the help of OCWs, a programmer can dynamically change the priority associatedwith each of IR0–IR7, or mask any of them.

    • Example 14-9 shows how OCWs are sent to the 8259.


14 3 8259 interrupt controller operation command word ocw48 l.jpg

14.3: 8259 INTERRUPT CONTROLLERoperation command word OCW

Three registers ofnote in the 8259:

ISR(in-serviceregister)

IRR(interruptrequest register)

IMR(interruptmask register)

Figure 14-4 Partial Block Diagram of the 8259A


14 3 8259 interrupt controller operation command word 1 ocw1 l.jpg

14.3: 8259 INTERRUPT CONTROLLERoperation command word 1 OCW1

OCW1 is used to mask any of IR0–IR7. Logic 1 is for masking. (disabling)

Logic 0 is for unmasking. (enabling)

Figure 14-7 OCW Format for 8259A


14 3 8259 interrupt controller operation command word 1 ocw150 l.jpg

14.3: 8259 INTERRUPT CONTROLLERoperation command word 1 OCW1

Figure 14-7 OCW Format for 8259A


14 3 8259 interrupt controller operation command word 2 ocw2 l.jpg

14.3: 8259 INTERRUPT CONTROLLERoperation command word 2 OCW2

  • OCW2 - used to assign a specific priority to the IRs.

    • Fully nested default mode - assigns the highestpriority to IR0 and the lowest to IR7.

      • 8259 can be programmed to change the defaultmode to assign the highest priority to any IR.

  • Specific rotation mode - 8259 can be programmed to make rotation follow a specific sequence rather thanIR0 to IR7.

    • The IR served will be stamped as the lowest priority, and willnot be served until every other request has had a chance.


14 3 8259 interrupt controller eoi end of interrupt command l.jpg

14.3: 8259 INTERRUPT CONTROLLEREOI end-of-interrupt command

  • Assume an 8259, initialized, in the default fully nested mode (IR0 has highest priority; IR7 lowest).

    • IR3 is activated, and the CPU acknowledges theinterrupt by sending back a signal through INTA.


14 3 8259 interrupt controller eoi end of interrupt command53 l.jpg

14.3: 8259 INTERRUPT CONTROLLEREOI end-of-interrupt command

  • Assume an 8259, initialized, in the default fully nested mode (IR0 has highest priority; IR7 lowest).

  • The CPU goes to the vector table and gets CS:IP of the interrupt service routine and starts to execute the routine.


14 3 8259 interrupt controller eoi end of interrupt command54 l.jpg

14.3: 8259 INTERRUPT CONTROLLEREOI end-of-interrupt command

  • Assume an 8259, initialized, in the default fully nested mode (IR0 has highest priority; IR7 lowest).

  • Issuing EOI to 8259 indicates IR3 servicing complete, and the bit associated with IR3 in ISR can be reset to zero


14 3 8259 interrupt controller eoi end of interrupt command55 l.jpg

14.3: 8259 INTERRUPT CONTROLLEREOI end-of-interrupt command

  • Assume an 8259, initialized, in the default fully nested mode (IR0 has highest priority; IR7 lowest).

  • The last three instructions of any interrupt service routine for IR0–IR7 must be issuing the EOI, followed by IRET.


14 3 8259 interrupt controller ocw3 l.jpg

14.3: 8259 INTERRUPT CONTROLLEROCW3

  • OCW3 is used read 8259 registers IRR (interrupt request register) & ISR (in-service register).

    • D0 and D1 allow the program to read these registersin order to see which of IR0–IR7 is pending for service and which one is being served.


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14.4: USE OF THE 8259 CHIP IN x86 PCs Interfacing 8259 to the IBM PC

Two port addresses must be assigned to the 8259:One for ICW1; the second for ICW2/ICW4.

Since the chip select is activatedby Y1 and all the x's for don't caremust be zero, the addresses canbe calculated in the mannershown.


14 4 use of the 8259 chip in x86 pcs 8259 initialization words in the pc l.jpg

14.4: USE OF THE 8259 CHIP IN x86 PCs 8259 initialization words in the PC

  • Configuration for the control words ICW1, ICW2, and ICW4 can be calculated:


14 4 use of the 8259 chip in x86 pcs 8259 initialization words in the pc59 l.jpg

INT 08 is for IRQ0, INT 09 is for IRQ1, etc.

14.4: USE OF THE 8259 CHIP IN x86 PCs 8259 initialization words in the PC

  • PC designers assigned INT 08–INT 0F for expansion of hardware interrupts.

    • Used by 8259 IR0–IR7, commonly called IRQ0–IRQ7.


14 4 use of the 8259 chip in x86 pcs 8259 initialization words in the pc60 l.jpg

14.4: USE OF THE 8259 CHIP IN x86 PCs 8259 initialization words in the PC

  • ICW2 informs 8259 which interrupt numbersare assigned to IRQ0–IRQ7.

    • By equating 8259 ICW2 to the interrupt assigned to IRQ0.

      • ICW2 is the interrupt number for IR0, in the IBM PC, INT08.

    • The 8259 is only programmed for the value of IRQ0, so the 8259 generates the INT numbers for IR1 through IR7.

  • ICW3 is used only when multiple 8259 chips are connected in master/slave mode.


14 4 use of the 8259 chip in x86 pcs 8259 initialization words in the pc61 l.jpg

14.4: USE OF THE 8259 CHIP IN x86 PCs 8259 initialization words in the PC

  • ICW4 configuration:

  • Gives the following code for 8259 initialization:


14 4 use of the 8259 chip in x86 pcs 8259 initialization l.jpg

14.4: USE OF THE 8259 CHIP IN x86 PCs 8259 initialization

  • Once the 8259 is initialized, it is ready toaccept an interrupt on any inputs IRQ0–IRQ7.

    • Expanding the number of hardware interrupts.

    • The 8259 is tested by a program in BIOS duringthe POST (power on self test).


14 4 use of the 8259 chip in x86 pcs sequences of 8259 hardware interrupts l.jpg

14.4: USE OF THE 8259 CHIP IN x86 PCs sequences of 8259 hardware interrupts

  • Sequence of events after an 8259 IR is activated.

    • 1. After an IR is activated, the 8259 will respond by putting a high on INTR.

      • Signaling the CPU for an interrupt request.

    • 2. 8088/86 puts the appropriate signals on S0, S1 & S2 (S0 = 0, S1 = 0, and S2 = 0), indicating to the 8288 that an interrupt has been requested.

    • 3. The 8288 issues the first INTA to the 8259.

    • 4. The 8259 receives the first INTA and does internal housekeeping, which includes resolution of priority, and resolution of cascading.

    • 5. The 8288 issues the second INTA to the 8259.


14 4 use of the 8259 chip in x86 pcs sequences of 8259 hardware interrupts64 l.jpg

14.4: USE OF THE 8259 CHIP IN x86 PCs sequences of 8259 hardware interrupts

  • Sequence of events after an 8259 IR is activated.

  • 6. On the second INTA pulse, 8259 puts a single interrupt vector byte on the data bus in which 8088/86 will latch. INTR.

    • The value of the single byte depends on ICW2 andwhich IR has been activated.

  • 7. 8088/86 uses this byte to calculate the vector location, which is four times the value of the INT type.


14 4 use of the 8259 chip in x86 pcs sequences of 8259 hardware interrupts65 l.jpg

14.4: USE OF THE 8259 CHIP IN x86 PCs sequences of 8259 hardware interrupts

  • Sequence of events after an 8259 IR is activated.

  • 8. 8088/86 pushes the flag register onto the stack, clears IF (Interrupt Flag) & TF (Trap Flag), disabling further external interrupt requests and single-step mode. INTR.

    • And pushes the present CS:IP registers onto the stack.

  • 9. The 8088/86 reads CS:IP of the interrupt service routine from the vector table and begins execution of the interrupt routine.


14 4 use of the 8259 chip in x86 pcs sources of hardware interrupts l.jpg

14.4: USE OF THE 8259 CHIP IN x86 PCs sources of hardware interrupts

  • With the 8259, the PC has eight interrupts.

    • IR0 to IR7, plus NMI of the 8088/86.

  • IBM has used two for internal use by the system.

    • IR0 - for channel 0 of the 8253 timer to updatethe time of day (TOD) clock,

    • IR1 - dedicated to the keyboard.

      • IR2 through IR7 are available through the expansion slots.

  • The following interrupts are used on the motherboard:

    • INT 08 IRQ0 Channel 0 of 8253 timer to update TOD

    • INT 09 IRQ1 Keyboard input data


14 4 use of the 8259 chip in x86 pcs sources of hardware interrupts67 l.jpg

14.4: USE OF THE 8259 CHIP IN x86 PCs sources of hardware interrupts

Figure 14-9PC Sources of Hardware Interrupts


14 4 use of the 8259 chip in x86 pcs sources of nmi l.jpg

14.4: USE OF THE 8259 CHIP IN x86 PCs sources of NMI

  • The NMI, nonmaskable interrupt, is a CPU pin, and cannot be masked (disabled) by software.

  • There are three sources of activation of the NMI:

    • 1. NPIRQ. (numerical processor interrupt request)

    • 2. Read/write PCK. (parity check)

    • 3. IOCHK. (input/output channel check)

  • The PC recognizes which of interrupt requests has been activated by checking input port C of the 8255.


14 4 use of the 8259 chip in x86 pcs sources of nmi69 l.jpg

14.4: USE OF THE 8259 CHIP IN x86 PCs sources of NMI

NMI is masked by a RESETsignal from the CPU withCLR of the D flip-flop whenthe computer is turned on.

Figure 14-10 Sources of NMI in the PC


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14.5: MORE ON INTERRUPTS IN x86 PCsx86 PC hardware interrupts

  • When the first PC was introduced, six hardware interrupts, IRQ2–IRQ7, were available throughthe 8-bit section of expansion slot.

    • IRQ0 and IRQ1, were used by the motherboard.

    • With the introduction of the 80286-based PC AT, another eight interrupts, IRQ8–IRQ15, were added.

  • In the second generation, designers had to ensureit was compatible with the 8088-based original PC.

    • Leading to use of IRQ0 & IRQ1 for the system timerand keyboard.


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14.5: MORE ON INTERRUPTS IN x86 PCsx86 PC hardware interrupts

  • IBM made the first 8259 a master, and added the second 8259 in slave mode.

    • Connecting INT pin of the slave 8259 toIRQ2 of the master 8259.

    • The master and slave 8259s communicate with each other through pins IRQ2, INT, CAS0, CAS1, and CAS2.


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14.5: MORE ON INTERRUPTS IN x86 PCsx86 PC hardware interrupts

  • On the ISA expansionslot, IRQ10, IRQ11,IRQ12, IRQ14, & IRQ15are on the 32-pin section.


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14.5: MORE ON INTERRUPTS IN x86 PCsx86 PC hardware interrupts

  • On the ISA expansionslot, IRQ9, IRQ3, IRQ4,IRQ5, IRQ6 & IRQ7 areon the 62-pin section.


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14.5: MORE ON INTERRUPTS IN x86 PCsx86 PC hardware interrupts

Figure 14-11 8259 Chips in Master/SlaveRelation for 286 and x86 PCs


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14.5: MORE ON INTERRUPTS IN x86 PCs x86 generated interrupts (exceptions)

  • Intel left the first 32 interrupts (INT 00 to INT 1FH) reserved for future microprocessors.

    • Designers of the first PC ignored this & assigned manyof them to system hardware/software interrupts.

  • By not adhering to Intel's specifications, IBM has created a massive headache for software designers of protected mode 386 and later systems.


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See the entire assignment chart on page 396 of your textbook.

14.5: MORE ON INTERRUPTS IN x86 PCs x86 generated interrupts (exceptions)

  • Intel continued to assign processor exception cases to INT 5 and higher with each new x86.


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In the x86, IRQ0 hasthe highest priority & IRQ7 is assigned the lowest priority.

14.5: MORE ON INTERRUPTS IN x86 PCs interrupt priority

  • Resolution of priority among IRQs is up to the 8259.

    • If both NMI & INTR are activated at the same time, NMIis first since NMI has a higher priority than INTR.

    • For the IRQs coming through INTR, the 8259 resolves priority depending on the way the 8259 is programmed.


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Since IRQ8 to IRQ15of the slave 8259 are connected to IRQ2 ofthe master 8259, they have higher prioritythan IRQ3 to IRQ7 ofthe master 8259.

14.5: MORE ON INTERRUPTS IN x86 PCs interrupt priority


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14.5: MORE ON INTERRUPTS IN x86 PCs level-triggered mode

  • In level triggered mode, 8259 will recognize a high on the IRQ input as an interrupt request.

    • The request must remain high until the first INTAis acknowledged from the 8259.

    • If the IRQ input remains high after the end ofinterrupt (EOI) command has been issued, the8259 will generate another interrupt on thesame IRQ input.


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14.5: MORE ON INTERRUPTS IN x86 PCs edge-triggered mode

  • In edge-triggered mode, 8259 will recognize an interrupt request only when a low-to-high pulse is applied to an IRQ input.

    • After the low-to-high transition on the IRQ input, 8259will acknowledge the interrupt request by activating INTA.

  • The IRR latch is disabled after the request is acknowledged, and will not latch another interrupt until that IRQ input goes back to low.

  • A disadvantage of edge-triggered mode is false interrupt caused by a spikes as a result of noiseon the IRQ line—especially in high-speed systems.


Slide81 l.jpg

Dec Hex Bin

14 E 00001110

ENDS ; FOURTEEN


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