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COS 250 Discrete Structures. Assoc. Prof. Svetla Boytcheva Spring semester 2011. Lecture № 10. Boolean Algebra. Boolean Functions Representing Boolean Functions Logic Gates Minimization of Circuits. Boolean Algebra.

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COS 250 Discrete Structures

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COS 250Discrete Structures

Assoc. Prof. Svetla Boytcheva

Spring semester 2011


Lecture № 10

Boolean Algebra


  • Boolean Functions

  • Representing Boolean Functions

  • Logic Gates

  • Minimization of Circuits


Boolean Algebra

The basic rules for simplifying and combining logic gates are called Boolean algebra in honour of George Boole (1815 – 1864) who was a self-educated English mathematician who developed many of the key ideas.


TABLE 1 (11.1)


NOT


AND


OR


FIGURE 1 (11.1)

FIGURE 1


TABLE 2 (11.1)


TABLE 3 (11.1)


x

f0

f1

f2

f3

0

1

0

0

0

1

1

0

1

1

n=1 - Boolean functions with 1 argument

f0(x)= const 0

f1 (x)=xidentity

f2 (x)= not xnegation (denotes like  xor)

f3 (x)= const 1


x y

f0

f1

f2

f3

f4

f5

f6

f7

f8

f9

f10

f11

f12

f13

f14

f15

0 0

0 1

1 0

1 1

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

n=2 - Boolean functions with 2 arguments

  • f0(x,y)=0;

  • f1(x,y)=x۸y - conjunction; (denotes like xy)

  • f3(x,y)=x;

  • f5(x,y)=y;


x y

f0

f1

f2

f3

f4

f5

f6

f7

f8

f9

f10

f11

f12

f13

f14

f15

0 0

0 1

1 0

1 1

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

n=2

f6(x,y)=xy

f7(x,y)=x v y -

f8 (x,y)=x↓y-Pears

f9(x,y)= xy –equivalence (xy or xy )


x y

f0

f1

f2

f3

f4

f5

f6

f7

f8

f9

f10

f11

f12

f13

f14

f15

0 0

0 1

1 0

1 1

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

n=2

  • f10(x,y)=not y;

  • f11(x,y)=y →x –reverse implication

  • f12(x,y)=not x

  • f13(x,y)=x →y –implication ‏


x y

f0

f1

f2

f3

f4

f5

f6

f7

f8

f9

f10

f11

f12

f13

f14

f15

0 0

0 1

1 0

1 1

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

n=2

f14(x,y)=x|y-Sheffer function

f15(x,y)=1;

f2 and f4not named - presents as


Sheffer stroke

In Boolean functions and propositional calculus, the Sheffer stroke, named after Henry M. Sheffer, written "|" or "↑", denotes a logical operation that is equivalent to the negation of the conjunction operation, expressed in ordinary language as "not both". It is also called the alternative denial, since it says in effect that at least one of its operands is false. In Boolean algebra and digital electronics it is known as the NAND operation ("not and").


Peirce arrow

Charles Sanders Peirce (September 10, 1839 – April 19, 1914) was an American philosopher, logician, mathematician, and scientist, born in Cambridge, Massachusetts. In 1880 he discovered how Boolean algebra could be done via a repeated sufficient single binary operation (logical NOR)

The Peirce arrow,symbol for "(neither)...nor...", also called the Quine dagger.


TABLE 4 (11.1)


TABLE 5 (11.1)

Boolean functions with 1 argument


TABLE 6 (11.1)


TABLE 1 (11.2)


TABLE 2 (11.2)


FIGURE 1 (11.3)

FIGURE 1 Basic Types of Gates.


XOR


NAND - NOR


AND, OR and NOT represented byNAND


Integral circuits


Примери


Decoder


Multiplexer


Example


FIGURE 2 (11.3)

FIGURE 2 Gates with n Inputs.


FIGURE 3 (11.3)

FIGURE 3 Two Ways to Draw the same Circuit.


FIGURE 4 (11.3)

FIGURE 4 Circuits that Produce the Outputs Specified in Example.


FIGURE 5 (11.3)

FIGURE 5 A Circuit for Majority Voting.


TABLE 1 (11.3)


FIGURE 6 (11.3)

FIGURE 6 A Circuit for a Light Controlled by Two Switches.


FIGURE 7 (11.3)

FIGURE 7 A Circuit for a Fixture Controlled by Three Switches.


TABLE 2 (11.3)

歐亞書局


TABLE 3 (11.3)


FIGURE 8 (11.3)

FIGURE 8 The Half Adder.


歐亞書局

FIGURE 9 (11.3)

FIGURE 9 A Full Adder.

P. 765


歐亞書局

TABLE 4 (11.3)

P. 765


歐亞書局

FIGURE 10 (11.3)

FIGURE 10 Adding Two Three-Bit Integers with Full and Half Adders.

P. 765


歐亞書局

FIGURE 1 (11.4)

FIGURE 1 Two Circuits with the Same Output.

P. 767


Useful Links

http://www.chem.uoa.gr/applets/appletgates/appl_gates2.html

http://www.ee.surrey.ac.uk/Projects/Labview/Sequential/Course/01-Decoder/index.htm

http://www.allaboutcircuits.com/vol_4/chpt_9/2.html

http://www.electronics-tutorials.ws/combination/comb_1.html


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