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Class Test. Batch 2013-2016 MM-15 Time: 30 min. 1. Design a typical stage that implement the following logic micro-operation 2. Construct a 5-to-32 line decoder with four 3-to-8 line decoders with enable and one 2-to-4 line decoder. 3. Write microperations for ISZ and Interrupt.

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class test

Class Test

Batch 2013-2016

MM-15 Time: 30 min

slide2

1. Design a typical stage that implement the following logic micro-operation

2. Construct a 5-to-32 line decoder with four 3-to-8 line decoders with enable and one 2-to-4 line decoder.

3. Write microperations for ISZ and Interrupt.

4. Draw the common bus architecture system for 30 processor registers where size of memory is 65, 536* 12.

a) What is the size of IR,PC,ACC,TR, AR, INP, OUT and other registers.

b) How many multiplexers are required also specify the size of each multiplexer.

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