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Performance Guarantees for Internet Routers ISL Affiliates Meeting April 4 th 2002. Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University [email protected] www.stanford.edu/~nickm. What a Router Looks Like. Cisco GSR 12416. Juniper M160. 19”.

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Performance Guarantees

for Internet Routers

ISL Affiliates Meeting

April 4th 2002

Nick McKeown

Professor of Electrical Engineering

and Computer Science, Stanford University

[email protected]

www.stanford.edu/~nickm


What a router looks like
What a Router Looks Like

Cisco GSR 12416

Juniper M160

19”

19”

Capacity: 160Gb/sPower: 4.2kW

Capacity: 80Gb/sPower: 2.6kW

6ft

3ft

2ft

2.5ft


Basic architectural components of an ip router
Basic Architectural Componentsof an IP Router

Routing

Protocols

Control Plane

Routing

Table

Datapath

per-packet

processing

Forwarding

Table

Switching


Generic router architecture

Data

Hdr

Data

Hdr

IP Address

Next Hop

Address

Table

Buffer

Memory

~1M prefixes

Off-chip DRAM

~1M packets

Off-chip DRAM

Generic Router Architecture

Header Processing

Lookup

IP Address

Update

Header

Queue

Packet


Generic router architecture1

Header Processing

Header Processing

Header Processing

Lookup

IP Address

Lookup

IP Address

Lookup

IP Address

Update

Header

Update

Header

Update

Header

Address

Table

Address

Table

Address

Table

Generic Router Architecture

Buffer

Manager

Buffer

Memory

Buffer

Manager

Buffer

Memory

Buffer

Manager

Buffer

Memory


High performance networking research group
High Performance Networking Research Group

  • Adisak Mekkitikul: Crossbar scheduling algorithms that provide 100% throughput.

  • Pankaj Gupta: IP address lookup and classification algorithms.

  • Sundar Iyer: Parallel packet switches; High performance packet buffers; Distributed shared memory routers.

  • Isaac Keslassy, Shang-tse Chuang: Incorporating optics into routers.

  • Pablo Molinero Fernandez: The use of circuit switching in the Internet.

  • Nandita Dukkipati, Rui Zhang: Congestion control for short-lived flows.

  • Yashar Ganjali: Multipath routing.

Graduated


Performance metrics of routers

WFQ

Performance metrics of routers

  • Capacity

    • “maximize C, s.t.volume < 2m3 and power < 5kW”

  • Throughput

    • Operators like to maximize usage of expensive long-haul links.

    • This would be trivial with work-conserving output-queued routers

  • Controllable Delay

    • Some users would like predictable delay.

    • This is feasible with output-queueing plus weighted fair queueing (WFQ).


The problem
The Problem

  • Output queued switches are impractical

R

R

R

R

DRAM

data

NR

NR


Memory bandwidth commercial dram
Memory BandwidthCommercial DRAM

  • It’s hard to keep up with Moore’s Law:

    • The bottleneck is memory speed.

    • Memory speed is not keeping up with Moore’s Law.

DRAM

1.1x / 18months

Moore’s Law

2x / 18 months

Router

Capacity

2.2x / 18months

Line Capacity

2x / 7 months


Potted history
Potted history

  • [Karol et al. 1987] Throughput limited to by head-of-line blocking for Bernoulli IID uniform traffic.

  • [Tamir 1989] Observed that with “Virtual Output Queues” (VOQs) Head-of-Line blocking is reduced and throughput goes up.


Potted history1
Potted history

  • [Anderson et al. 1993] Observed analogy to maximum size matching in a bipartite graph.

  • [M et al. 1995] (a) Maximum size match can not guarantee 100% throughput.(b) But maximum weight match can – O(N3).

  • [Mekkittikul and M 1998] A carefully picked maximum size match can give 100% throughput.

Matching

O(N2.5)


Potted history speedup
Potted history Speedup

5. [Chuang, Goel et al. 1997] Precise emulation of an output queued switch is possible with a speedup of two and a “stable marriage” scheduling algorithm.

  • [Prabhakar and Dai 2000] 100% throughput possible for maximal matching with a speedup of two.


Potted history newer approaches
Potted historyNewer approaches

  • [Tassiulas 1998] 100% throughput possible for simple randomized algorithm with memory.

  • [Giaccone et al. 2001] “Apsara” algorithms.

  • [Iyer and M 2000] Parallel switches can achieve 100% throughput and emulate an output queued switch.

  • [Chang et al. 2000] A 2-stage switch with a TDM scheduler can give 100% throughput.

  • [Iyer, Zhang and M 2002] Distributed shared memory switches can emulate an output queued switch.


Basic switch model
Basic Switch Model

S(n)

L11(n)

A11(n)

1

1

D1(n)

A1(n)

A1N(n)

AN1(n)

DN(n)

AN(n)

N

N

ANN(n)

LNN(n)


Some definitions
Some definitions

3. Queue occupancies:

Occupancy

L11(n)

LNN(n)


Some definitions of throughput
Some definitions of throughput

When traffic is admissible


Scheduling algorithms to achieve 100 throughput
Scheduling algorithms to achieve 100% throughput

  • When traffic is uniform (Many algorithms…)

  • When traffic is non-uniform, but traffic matrix is known

    • Technique: Birkhoff-von Neumann decomposition. [Chang ‘99]

  • When matrix is not known.

    • Technique: Lyapunov function. [M et al. ‘96]

  • When algorithm is pipelined, or information is incomplete.

    • Technique: Lyapunov function. [Keslassy & M ’01]

  • When algorithm does not complete.

    • Technique: Randomized algorithm. [Tassiulas ’00]

  • When there is speedup.

    • Technique: Fluid model. [Dai & Prabhakar ’00]

  • When there is no algorithm.

    • Technique: 2-stage load-balancing switch. [Chang ’01]

    • Technique: Parallel Packet Switch. [Iyer & M ’01]



Throughput results

Different weight functions,

incomplete information, pipelining.

IQ + VOQ,

Maximum weight matching

100% [Various]

Randomized algorithms

100% [Tassiulas, 1998]

100% [M et al., 1996]

IQ + VOQ,

Maximal size matching,

Speedup of two.

100% [Dai & Prabhakar, 2000]

IQ + VOQ,

Sub-maximal size matching

e.g. PIM, iSLIP.

Throughput results

Theory:

Input

Queueing

(IQ)

58% [Karol, 1987]

Practice:

Input

Queueing

(IQ)

Various heuristics, distributed algorithms,

and amounts of speedup


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