1 / 20

Digital Logic Design

Digital Logic Design. Lecture # 14 University of Tehran. Outline. Review of Lecture #13 PLA PAL Structure of PROM’s Transistors MSI Parts as a ROM Cascading ROMs. Review of Lecture #13.

clinton-dawson
Download Presentation

Digital Logic Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Digital Logic Design Lecture # 14 University of Tehran

  2. Outline • Review of Lecture #13 • PLA • PAL • Structure of PROM’s Transistors • MSI Parts as a ROM • Cascading ROMs

  3. Review of Lecture #13 • Let us continue our discussion of programmable devices. We saw the structure of a ROM with 4 inputs that had 16 lines entering its OR plane from the AND plane. The AND plane can actually be considered a 4-to-16 DCD as seen in the following figure:

  4. Review of Lecture #13 (continued…) • We saw that no minimization was done when realizing functions with ROMs, because all minterms were produced in the fixed AND plane.

  5. PLA • Consider the following truth table:

  6. PLA (continued…) • Note all minterms are used in the realization of a function, and so minimizing this truth table using 4 variable KMs can be useful. Consider the following minimization:

  7. PLA (continued…) • In the minimization method shown in the last slide, the number of variables used in a term is of no importance. What we are looking to do in this minimization is to share product terms between the different functions thus being able to decrease the number of rows in our AND plane. Doing this the shown truth table can be realized as shown in the next slide.

  8. PLA (continued…)

  9. PLA (continued…) • The reason we don’t look for decreasing the number of literals in our product terms is rather obvious as there is no hardware difference. What we gain in this procedure is better layout and less rows which can be better observed in functions of a larger number of variables. These structures are called PLAs.

  10. PLA (continued…) • We should see PLAs as structured logic components helping us with a reduction of size in comparison to the more general-purposed ROM ICs. • Nowadays PLA programmers use other techniques such as column sharing in order to decrease the size of PLAs even more.

  11. PAL • There is also a third kind of programmable device with a fixed OR plane and a programmable AND plane. An example of this structure called a PAL structure can be seen below:

  12. PAL (continued…) • As you can see in the last figure, PALs give us the ability to share certain product terms between two particular functions. Another choice PALs give us in order to realize larger functions in the ability to feedback an output of an OR gate back into the AND plane and use it as a part of a larger function. It must be noted that a feedback line can itself be used as an output.

  13. PAL (continued…) • PALs do have a benefit with respect to PLAs alongside all the restrictions they bring for realization of a function and that is better timing. This is because there is less delay on the OR gates of a PLA because of the fixed and rather small number of inputs to each OR gate.

  14. Structure of PROM’s Transistors • Let’s see the kind of transistors that are used in PROMs. These transistors are called floating gate transistors and are structured as shown below:

  15. Structure of PROM’s Transistors (continued…) • When such a transistor is to be disabled the floating gate is given a high voltage that brings electrons from the two diffusion areas into it, giving it a negative charge and thus disabling the gate. Ultra violet light can be used to send these electrons back to the diffusion area.

  16. MSI Parts as a ROM • Let’s consider a 2764: In this figure the VPP and PFM pins are used when programming the package. This package has 13 inputs that gives us 213*8 memory locations. That is 213 addresses pointing to 8 bit words.

  17. MSI Parts as a ROM (continued…) • The output lines are also used as input lines with the use of three state buffers as can be seen. When both CS and OE signals are 0, these pins act as output and otherwise can be inputs for programming.

  18. Cascading ROMs • Standard packages need to have the ability to cascade. ROMs are cascaded in 2 styles: • The following method is called horizontal cascading that expands our word length:

  19. Cascading ROMs (continued…) • The other one is called vertical cascading that expands our address space to 14 lines that is 16k, as shown in the following figure:

  20. Cascading ROMs (continued…) • Note that the programming of these packages must be done each on its own and not in cascaded form.

More Related