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Different cap. load

Proposal for the read out system for the future Si. Vertex Detector with signal processing and hit data production for a fast track trigger ? M. Pernicka.

clayton-bryan
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Different cap. load

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  1. Proposal for the read out system for the future Si. Vertex Detector with signal processing and hit data production for a fast track trigger ? M. Pernicka

  2. Theoretical time window for the trigger working with 40 MHz for the ADC, in reality more wide continuous beam trigger and clock no more synchronic 25 ns or less Different cap. load Pulse shape of the second step ns The pulse shape could be smaller – less occupancy

  3. Output of the APV25 128 output signals Analogous signal hit 1mA/mip ideal case 12 cl. 128 clocks Critical point for the digitization. clock must be well adjusted for every input as well as possible. You cannot aspect a flat range repeater must have a good frequency behaviour After L0 < 160 (180) clock pulses distance to the event and < 3,8µs after L0 25 ns or less Depends of frequency

  4. AC toppling between APV25 and ADC with base line restore

  5. Every input has its own data processor. The programme to find hits in the data stream of the APV25 could be from the CMS group or us ? The hit data with the position will be ready at the same time for all inputs. The processing needs the same time as the read out . Unlimited for the trigger rate (limit the APV25 and data transfer to the DAQ.

  6. One module digitice and looks for hits for trigger proc. Most simple version. Final data block for one input L0 ADC APV25 +…... 1 proc. FIFO 128 2 proc. FIFO n*128 Reorder the data and combine ? stripes after reorder of channels(?) Serial data output Compare Data with Ped+ Threthhold for the trigger proc. ADC APV25 +…... 1 proc. 2 proc. FIFO n*128 FIFO 128 Reorder the data and combine ? stripes after reorder of channels (?) Serial data output Compare Data with Ped+ Threthhold for the trigger proc. 12 12 128 Data 128 Data 2 event data block just behind each other 6*1+2*0 = start f. e. not possible in the data stream 1 hit 2 hits Trigger data, serial 40 MHz or more Hephy Vienna Manfred Pernicka

  7. A possibility to process the Data of the APV25 in 2 Steps. Every input has its own processor! The final `` program `` has to be found or we will use that of CMS for their Vertex Det. signal finding. Data from hits + neighbours and position APV25 ADC FIFO for data Serial Out put for trigger processor (Corrected serial output for trigger processor) Comparator Comparator Corrected Ped(var) for one event + threshold Memory ped(con) + threshold (Sum of in input data below ped. + ped. of data above of ped) / 128 – sum ped(cor)/128 = correction factor Hephy Vienna Manfred Pernicka

  8. It would be possible to create a trigger with a fixed delay to the event in steps of a clock. For that we have to create special trigger rules f.e. no more than 2 trigger in a certain time window Ev 1 2 3 4*70*25ns or less Module y Module x Hit data ready for trigger event 1 Hit data ready for trigger event 2 140*25ns or less Trigger in phase trigger in phase Hephy Vienna Manfred Pernicka

  9. Track trigger created from Si vertex data • Advantage: Hit efficiency high nearly 100% • Hit data are ready just after read APV25 • Delay between trigger and the first data in the range 2,9µ to 3,79µs for 40 MHz. • Delay between trigger and the last data in the range 6.4µs to 7.29µs for 40 MHz • Depends of clock- fr. For 60 Mhz 2/3 of the time • low noise: depends of dig. threshold setting • track trigger resolution depends of granularity • Quality and efficiency depends of the lay out of the Si det. • Possible holes which we cannot cover-reduces the efficiency • Problems: For a synchr. Trigger: The trigger for the APV25 needs a limitation in the case • that we want a time stable trigger with a fixed delay to the trigger • Has to be calculated. • The time fluctuation for read out can be corrected afterwards to a fixed value. We know • the time jitter. Hephy Vienna Manfred Pernicka

  10. Proposal for the ADC System for the Si. Vertex Det. BELLE. A, The APV25 should be driven with a clock frequency as high as possible The limits are a possible reduction of S/N and there is no guaranty that ``all`` APV25 have the same limit in speed! Fluctuation in production. Advantages: More trigger/ sec are possible because faster read out and the time distance between 2 trigger becomes smaller. (Less jitter of the trigger to the shaped analogue signal.) The hit information for the trigger arrives faster. A frequency up to 80 MHz could be possible. Disadvantages: The signals from the APV25 are short. From 25ns to 12.5ns. The time range to be used for digitations in the ADC is extreme small. Therefore the clock for the ADC must be adjusted for every channel. The data transmission between REBRO and ADC module must be fast (C-coupling) The ADC-SP can adjust for every input the phase of the clock. Steps are around 1,6ns or less. B,There should be no limitfor the trigger rate and time for data processing and storing The ADC-TF2 has for every input a 2 step hit finding processor. The program could be more or less the same like it is used for CMS. Complete pipe line. The processed data from every input are ready at the same time. For the trigger data the first processor is used. The trigger data are ready just after the read out from the APV25 at the same time for all inputs. As output the VME P2 connector is used. (The step 2 processor would need the same time like step 1 Pr).. Hephy Vienna Manfred Pernicka

  11. Trigger proc. COPPER ??? Trigger lines from some ADC modules 9 U V M E From every input a serial trigger data output ? buffer Event data block from all inputs 64 bit data - 2 hits (36 at the moment) S-link or ???

  12. Multiplexing of Strip Channels of APV25 Stage 1 CLK/16 Stage 2 CLK/4 Stage 3 CLK 0,1,2,... 0 81 … 7 0,8,16,24 | 1,9,17,25 | 2,10,... 8,9,10,... 8 81 … 41 0,32,64,96 | 8,40,72,104 | 16,48,80,112 | 24,56,88,120 || 1,33,65,97 | 9,... 15 16,17,18,... 16 81 … 23 24,25,26,... 24 81 … 32,40,48,56 | 33,41,49,57 | 34,42,... 41 31 32 … 63 64,72,80,88 | 65,... 64 … 95 96,104,112,120 | 97,... 96 … 127 For the trigger processor the data should be ordered. 4,8 or Si. Stripes will be combined. Hephy Vienna Manfred Pernicka

  13. Some words about the Pixel read out system of approximate 40 Mil. pixel for CMS. What exist. What we can use. What has to be changed.

  14. Schematic of the ADC-Pixel with the possibility of single channel processing and output with data for trigger processor. (more or less exists) TTC input optical connection VME protocol Altera 4 times 10 bit data P 1 4 clocks with different phase 9 lines with information for trigger 12 input opt 4 ADC Altera Daughter 9 inputs with 2 steps of FIFO 64 (or 32 bit) bit data bus 40 MHz+4 control Data for trigger P 2 TTC Altera daughter with final FIFO 8 clocks with different phase + condole signal 2 clocks phase shifted P 3 Fast data transfer to PCI Hephy Vienna Manfred Pernicka

  15. 19 mm Proposed: ADC module with 36 (and hope 40) Inputs mainly build by daughter cards ( now 9 ADC card , 10 may be space problem) ADC module with 36 inputs ( only daughter cards on 1 side is now in construction for CMS pixel read out system. The reason for only 36 is , that the data flow to the DQS over a S-link is already around 400 MHz Byte. The prototype without firmware is ready since 2004-3. (serial outputs for trigger information are foreseen. ) 4 Daughter cards with Altera for signal processing and memory Daughter card with final multi event memory 9 Daughter cards with 4 ADC 10 bit may be it has to be modified Would be critical 9 daughter cards with 4 ADC or we use also the mother card for ADC’s Hephy Vienna Manfred Pernicka

  16. Principe of the ADC for pixel read out with opt. inputs (now in construction nearly finished) Link from opt. Receiver to TTCrx TW cable 2 32+5 Address- comp Opt.receiver En for link DAC test Buf.+ gate clockenabel locbus1 30 Loadbus1 6 TW 15*128*32 20 events FIFO2 8K*72 1in 15*128*32 FIFO1 2in 6*128*32 3in 6*128*32 loadbus2 12 inputopto A D C+A m p+T I m I N g+T e S t f a S I 90 da FIFo ERROR 5 V M E (2 buses to load Altera) 9 FIFO2 8K*72 5 I2C 9in 6*128*32 32+5 locbus2 9 cl FIFO ERROR 2 I2C Buffer for36 out puts trig LVDS limit in pins may be single output 9 when possible or 6 64+5 1 3 2K*72 spy. 15*128*32 20 events 90 64+5 FIFO 8K*72 12 inputopto 6 9 M u l tipl Strobe-Buf 6 2 2 2 12 12 8 8 Clock buffer switch and symmetr. 1 Delay Altera 70x 12 71 - 75 S- L Ink Buf Delay TTrx 1 55 2 6 64+5 Clo 80 MHz 12 inputo 15*128*32 20 events Hephy Vienna Manfred Pernicka TTS 2 24 4 TTS-Buf Ext Clo.+ Test optoparametabus Buf

  17. Layout for the daughter card of the Altera EP1S20_F672 with EPROM and Voltage regulator (exist) Voltage regulator EPROM We can use 360 input/output That limits the number of ADC (one ADC min. 8+1) Every output is serial terminated Altera side elevation 14 mm ADC version for pixel read out Hephy Vienna Manfred Pernicka

  18. 4 connestors, each with 100 pins

  19. 4 ADC and test system on one card

  20. Module to test ADC- and Altera daughter card Daughter card with 4 inputs ADC Daughter card with Altera Delay IC’s PHOS-4 Long transmission line serially terminated study of pulse deformation Hephy Vienna Manfred Pernicka

  21. Final ADC module for the pixel system Optical link Opt. input for TTC Optical receiver TTCrx 36 outputs with seriell hit data S-link or

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